| v {xschem version=2.9.8 file_version=1.2} |
| K {type=subcircuit |
| format="@name @pinlist @symname" |
| template="name=x1" |
| } |
| |
| T {@symname} -49.5 -6 0 0 0.3 0.3 {} |
| T {@name} 135 -72 0 0 0.2 0.2 {} |
| L 4 -130 -60 130 -60 {} |
| L 4 -130 60 130 60 {} |
| L 4 -130 -60 -130 60 {} |
| L 4 130 -60 130 60 {} |
| B 5 -152.5 -52.5 -147.5 -47.5 {name=clk dir=in name=p2 } |
| L 4 -150 -50 -130 -50 {} |
| T {clk} -125 -54 0 0 0.2 0.2 {} |
| B 5 -152.5 -32.5 -147.5 -27.5 {name=addr1[4:0] dir=in name=p3 } |
| L 4 -150 -30 -130 -30 {} |
| T {addr1[4:0]} -125 -34 0 0 0.2 0.2 {} |
| B 5 -152.5 -12.5 -147.5 -7.5 {name=addr2[4:0] dir=in name=p5 } |
| L 4 -150 -10 -130 -10 {} |
| T {addr2[4:0]} -125 -14 0 0 0.2 0.2 {} |
| B 5 147.5 -52.5 152.5 -47.5 {name=data1[31:0] verilog_type=reg dir=out name=p6 } |
| L 4 130 -50 150 -50 {} |
| T {data1[31:0]} 125 -54 0 1 0.2 0.2 {} |
| B 5 -152.5 7.5 -147.5 12.5 {name=rw dir=in name=p8 } |
| L 4 -150 10 -130 10 {} |
| T {rw} -125 6 0 0 0.2 0.2 {} |
| B 5 147.5 -32.5 152.5 -27.5 {name=data2[31:0] verilog_type=reg dir=out name=p7 } |
| L 4 130 -30 150 -30 {} |
| T {data2[31:0]} 125 -34 0 1 0.2 0.2 {} |
| B 5 -152.5 27.5 -147.5 32.5 {name=addr3[4:0] dir=in name=p4 } |
| L 4 -150 30 -130 30 {} |
| T {addr3[4:0]} -125 26 0 0 0.2 0.2 {} |
| B 5 -152.5 47.5 -147.5 52.5 {name=wdata[31:0] dir=in name=p1 } |
| L 4 -150 50 -130 50 {} |
| T {wdata[31:0]} -125 46 0 0 0.2 0.2 {} |
