| commit | f277036790028f5f9c61e1261d1f1e0c0828a275 | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Thu Mar 17 21:09:02 2022 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Thu Mar 17 21:09:02 2022 +0000 |
| tree | 96c874760a0b53948448dd2d987b822f0176e5bb | |
| parent | b3ac77dd3737f2aa461199484538fd91c363deed [diff] |
add gds/lef/rtl
Demonstration of the fully open FABulous eFPGA using the OpenLane flow.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.