| # SPDX-FileCopyrightText: 2020 Efabless Corporation |
| # |
| # Licensed under the Apache License, Version 2.0 (the "License"); |
| # you may not use this file except in compliance with the License. |
| # You may obtain a copy of the License at |
| # |
| # http://www.apache.org/licenses/LICENSE-2.0 |
| # |
| # Unless required by applicable law or agreed to in writing, software |
| # distributed under the License is distributed on an "AS IS" BASIS, |
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # See the License for the specific language governing permissions and |
| # limitations under the License. |
| # |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| ## PDK |
| PDK_PATH = $(PDK_ROOT)/sky130A |
| |
| ## Caravel Pointers |
| CARAVEL_ROOT ?= ../../../../caravel |
| CARAVEL_PATH ?= $(CARAVEL_ROOT) |
| |
| CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog |
| CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl |
| CARAVEL_MGMT_VERILOG_PATH = $(CARAVEL_PATH)/mgmt_core_wrapper/verilog |
| CARAVEL_MGMT_RTL_PATH = $(CARAVEL_MGMT_VERILOG_PATH)/rtl |
| CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel |
| |
| ## User Project Pointers |
| UPRJ_VERILOG_PATH ?= ../../../../verilog |
| UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl |
| UPRJ_BEHAVIOURAL_MODELS = ../ |
| |
| POWERPC_CROSS_COMPILE?=powerpc64le-linux-gnu- |
| POWERPC_CFLAGS=-static -Os -g -Wall -std=c99 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -ffreestanding -fdata-sections -ffunction-sections -nostdlib -I../include |
| |
| ## Simulation mode: RTL/GL |
| SIM_DEFINES = -DFUNCTIONAL -DSIM |
| SIM?=RTL |
| |
| .SUFFIXES: |
