merged main
diff --git a/.gitignore b/.gitignore
index f4e486c..9ccca4b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,5 @@
-precheck_results
\ No newline at end of file
+precheck_results
+*.hex*
+*.lst
+*.vcd
+*.gtkw
diff --git a/Makefile b/Makefile
index 6ca4b99..79515c7 100644
--- a/Makefile
+++ b/Makefile
@@ -16,6 +16,7 @@
CARAVEL_ROOT?=$(PWD)/caravel
PRECHECK_ROOT?=${HOME}/mpw_precheck
+MCW_ROOT?=$(PWD)/mgmt_core_wrapper
SIM ?= RTL
# Install lite version of caravel, (1): caravel-lite, (0): caravel
@@ -53,13 +54,22 @@
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
TARGET_PATH=$(shell pwd)
VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
-$(DV_PATTERNS): verify-% : ./verilog/dv/%
+
+.PHONY: dv_all
+dv_all:$(DV_PATTERNS)
+
+$(DV_PATTERNS): verify-% : ./verilog/dv/% check-env
docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
- -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
- -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
- -e CARAVEL_ROOT=${CARAVEL_ROOT} \
- -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
- sh -c $(VERIFY_COMMAND)
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -e TOOLS=/opt/riscv32i \
+ -e DESIGNS=$(TARGET_PATH) \
+ -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \
+ -e GCC_PREFIX=riscv32-unknown-elf \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
# Openlane Makefile Targets
BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
diff --git a/caravel b/caravel
deleted file mode 160000
index 793bf63..0000000
--- a/caravel
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 793bf634c2c1b1af90be95fcd85688e869bfb667
diff --git a/docs/source/roundtrip.rst b/docs/source/roundtrip.rst
index 298cccf..eaeb478 100644
--- a/docs/source/roundtrip.rst
+++ b/docs/source/roundtrip.rst
@@ -49,7 +49,7 @@
git checkout -b <my_branch>
git push -u origin <my_branch>
-4. Now that your git environment is setup, it's time to setup your local environment
+4. Now that your git environment is setup, it's time to setup your local environment. (NOTE: docker is a prerequisite to setting up your environment)
.. code:: bash
@@ -69,6 +69,7 @@
# Build the pdk
# make sure to change <directory_name> with the directory you created in step 1
# in this case it is caravel_tutorial
+
export PDK_ROOT=~/<directory_name>/pdks # you need to export this whenever you start a new shell
make pdk
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index d87238f..d151b60 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,9 +19,11 @@
.SUFFIXES:
.SILENT: clean all
+
PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
all: ${PATTERNS}
+
for i in ${PATTERNS}; do \
( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
done
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
index 5237a05..3fd0b56 100644
--- a/verilog/dv/io_ports/Makefile
+++ b/verilog/dv/io_ports/Makefile
@@ -14,83 +14,19 @@
#
# SPDX-License-Identifier: Apache-2.0
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
+# ---- Include Partitioned Makefiles ----
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
+CONFIG = caravel_user_project
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-.SUFFIXES:
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-PATTERN = io_ports
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c
index 0b23571..aa111ef 100644
--- a/verilog/dv/io_ports/io_ports.c
+++ b/verilog/dv/io_ports/io_ports.c
@@ -16,8 +16,8 @@
*/
// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
/*
IO Test:
@@ -46,7 +46,11 @@
/* Set up the housekeeping SPI to be connected internally so */
/* that external pin changes don't affect it. */
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // reg_spi_enable = 1;
+ // reg_spimaster_cs = 0x10001;
+ // reg_spimaster_control = 0x0801;
+
+ // reg_spimaster_control = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
// Connect the housekeeping SPI to the SPI master
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
index f7628bc..4e526ba 100644
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ b/verilog/dv/io_ports/io_ports_tb.v
@@ -17,9 +17,9 @@
`timescale 1 ns / 1 ps
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
+// `include "uprj_netlists.v"
+// `include "caravel_netlists.v"
+// `include "spiflash.v"
module io_ports_tb;
reg clock;
@@ -28,15 +28,15 @@
reg power1, power2;
reg power3, power4;
- wire gpio;
- wire [37:0] mprj_io;
+ wire gpio;
+ wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
assign mprj_io_0 = mprj_io[7:0];
// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
- // assign mprj_io[3] = 1'b1;
+ // assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ // assign mprj_io[3] = CSB;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -69,18 +69,18 @@
initial begin
// Observe Output pins [7:0]
- wait(mprj_io_0 == 8'h01);
- wait(mprj_io_0 == 8'h02);
- wait(mprj_io_0 == 8'h03);
- wait(mprj_io_0 == 8'h04);
- wait(mprj_io_0 == 8'h05);
- wait(mprj_io_0 == 8'h06);
- wait(mprj_io_0 == 8'h07);
- wait(mprj_io_0 == 8'h08);
- wait(mprj_io_0 == 8'h09);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'hFF);
- wait(mprj_io_0 == 8'h00);
+ wait(mprj_io_0 == 8'h01);
+ wait(mprj_io_0 == 8'h02);
+ wait(mprj_io_0 == 8'h03);
+ wait(mprj_io_0 == 8'h04);
+ wait(mprj_io_0 == 8'h05);
+ wait(mprj_io_0 == 8'h06);
+ wait(mprj_io_0 == 8'h07);
+ wait(mprj_io_0 == 8'h08);
+ wait(mprj_io_0 == 8'h09);
+ wait(mprj_io_0 == 8'h0A);
+ wait(mprj_io_0 == 8'hFF);
+ wait(mprj_io_0 == 8'h00);
`ifdef GL
$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
@@ -123,30 +123,36 @@
wire flash_io0;
wire flash_io1;
- wire VDD3V3 = power1;
- wire VDD1V8 = power2;
- wire USER_VDD3V3 = power3;
- wire USER_VDD1V8 = power4;
- wire VSS = 1'b0;
+ wire VDD3V3;
+ wire VDD1V8;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
.vssio (VSS),
+ .vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
- .vdda1 (USER_VDD3V3),
- .vdda2 (USER_VDD3V3),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
.vssa1 (VSS),
+ .vssa1_2 (VSS),
.vssa2 (VSS),
- .vccd1 (USER_VDD1V8),
- .vccd2 (USER_VDD1V8),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
- .clock (clock),
+ .clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
index ba979f7..3fd0b56 100644
--- a/verilog/dv/la_test1/Makefile
+++ b/verilog/dv/la_test1/Makefile
@@ -14,83 +14,19 @@
#
# SPDX-License-Identifier: Apache-2.0
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
+# ---- Include Partitioned Makefiles ----
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
+CONFIG = caravel_user_project
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-.SUFFIXES:
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-PATTERN = la_test1
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
index 220bdfe..96b56bd 100644
--- a/verilog/dv/la_test1/la_test1.c
+++ b/verilog/dv/la_test1/la_test1.c
@@ -16,8 +16,8 @@
*/
// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
// --------------------------------------------------------
@@ -31,11 +31,17 @@
void main()
{
+ int j;
/* Set up the housekeeping SPI to be connected internally so */
/* that external pin changes don't affect it. */
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // reg_spi_enable = 1;
+ // reg_spimaster_cs = 0x00000;
+
+ // reg_spimaster_control = 0x0801;
+
+ // reg_spimaster_control = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
// Connect the housekeeping SPI to the SPI master
@@ -88,19 +94,19 @@
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
// Set UART clock to 64 kbaud (enable before I/O configuration)
- reg_uart_clkdiv = 625;
+ // reg_uart_clkdiv = 625;
reg_uart_enable = 1;
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
+ // Now, apply the configuration
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
- // Configure LA probes [31:0], [127:64] as inputs to the cpu
+ // Configure LA probes [31:0], [127:64] as inputs to the cpu
// Configure LA probes [63:32] as outputs from the cpu
- reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
// Flag start of the test
reg_mprj_datal = 0xAB400000;
@@ -109,10 +115,10 @@
reg_la1_data = 0x00000000;
// Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
+ reg_la1_oenb = reg_la1_iena = 0x00000000;
while (1) {
- if (reg_la0_data > 0x1F4) {
+ if (reg_la0_data_in > 0x1F4) {
reg_mprj_datal = 0xAB410000;
break;
}
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
index 626e390..81a4e32 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/la_test1/la_test1_tb.v
@@ -17,10 +17,10 @@
`timescale 1 ns / 1 ps
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "tbuart.v"
+// `include "uprj_netlists.v"
+// `include "caravel_netlists.v"
+// `include "spiflash.v"
+// `include "tbuart.v"
module la_test1_tb;
reg clock;
@@ -29,9 +29,9 @@
reg power1, power2;
- wire gpio;
+ wire gpio;
wire uart_tx;
- wire [37:0] mprj_io;
+ wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
@@ -43,14 +43,14 @@
clock = 0;
end
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ // assign mprj_io[3] = 1'b1;
initial begin
- // $dumpfile("la_test1.vcd");
- // $dumpvars(0, la_test1_tb);
+ $dumpfile("la_test1.vcd");
+ $dumpvars(0, la_test1_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (200) begin
+ repeat (250) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
@@ -69,6 +69,7 @@
$display("LA Test 1 started");
wait(checkbits == 16'hAB41);
wait(checkbits == 16'hAB51);
+ $display("LA Test 2 passed");
#10000;
$finish;
end
@@ -91,37 +92,44 @@
power2 <= 1'b1;
end
- wire flash_csb;
+ wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD1V8;
- wire VDD3V3;
+ wire VDD3V3;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
+ assign mprj_io[3] = 1; // Force CSB high.
+ assign mprj_io[0] = 0; // Disable debug mode
+
caravel uut (
.vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
.vssio (VSS),
+ .vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
+ .vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
- .clock (clock),
+ .clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
index 0435500..3fd0b56 100644
--- a/verilog/dv/la_test2/Makefile
+++ b/verilog/dv/la_test2/Makefile
@@ -14,83 +14,19 @@
#
# SPDX-License-Identifier: Apache-2.0
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
+# ---- Include Partitioned Makefiles ----
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
+CONFIG = caravel_user_project
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-.SUFFIXES:
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-PATTERN = la_test2
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/la_test2/la_test2.c b/verilog/dv/la_test2/la_test2.c
index 5875432..25fad48 100644
--- a/verilog/dv/la_test2/la_test2.c
+++ b/verilog/dv/la_test2/la_test2.c
@@ -16,8 +16,8 @@
*/
// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
/*
MPRJ LA Test:
@@ -34,7 +34,8 @@
/* Set up the housekeeping SPI to be connected internally so */
/* that external pin changes don't affect it. */
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ reg_spi_enable = 1;
// connect to housekeeping SPI
// Connect the housekeeping SPI to the SPI master
@@ -83,16 +84,16 @@
while (reg_mprj_xfer == 1);
// Configure All LA probes as inputs to the cpu
- reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
// Flag start of the test
reg_mprj_datal = 0xAB600000;
// Configure LA[64] LA[65] as outputs from the cpu
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC;
+ reg_la2_oenb = reg_la2_iena = 0x00000003;
// Set clk & reset to one
reg_la2_data = 0x00000003;
@@ -106,9 +107,14 @@
reg_la2_data = 0x00000000 | clk;
}
- if (reg_la0_data >= 0x05) {
- reg_mprj_datal = 0xAB610000;
- }
+ // reg_mprj_datal = 0xAB610000;
+
+ while (1){
+ if (reg_la0_data_in >= 0x05) {
+ reg_mprj_datal = 0xAB610000;
+ break;
+ }
+
+ }
}
-
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v
index e09905e..168664b 100644
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ b/verilog/dv/la_test2/la_test2_tb.v
@@ -17,9 +17,9 @@
`timescale 1 ns / 1 ps
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
+// `include "uprj_netlists.v"
+// `include "caravel_netlists.v"
+// `include "spiflash.v"
module la_test2_tb;
reg clock;
@@ -28,12 +28,11 @@
reg power1, power2;
- wire gpio;
- wire [37:0] mprj_io;
+ wire gpio;
+ wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
always #12.5 clock <= (clock === 1'b0);
@@ -46,7 +45,7 @@
$dumpvars(0, la_test2_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (30) begin
+ repeat (75) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
@@ -61,20 +60,18 @@
end
initial begin
- wait(checkbits == 16'h AB60);
+ wait(checkbits == 16'hAB60);
$display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
- wait(checkbits == 16'h AB61);
+ wait(checkbits == 16'hAB61);
$display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
$finish;
end
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
+ #1000;
+ RSTB <= 1'b1; // Release reset
#2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
end
initial begin // Power-up sequence
@@ -99,24 +96,31 @@
assign VDD1V8 = power2;
assign VSS = 1'b0;
+ assign mprj_io[3] = 1; // Force CSB high.
+ assign mprj_io[0] = 0; // Disable debug mode
+
caravel uut (
.vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
.vssio (VSS),
+ .vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
+ .vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
- .clock (clock),
+ .clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index b0e4051..3fd0b56 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -14,88 +14,19 @@
#
# SPDX-License-Identifier: Apache-2.0
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
-## Management SoC Pointers
-MGMT_SOC_PATH ?= ../../../../caravel_pico
-MGMT_SOC_VERILOG_PATH = $(MGMT_SOC_PATH)/verilog
-MGMT_SOC_RTL_PATH = $(MGMT_SOC_PATH)/verilog/rtl
+# ---- Include Partitioned Makefiles ----
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
+CONFIG = caravel_user_project
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-.SUFFIXES:
-PATTERN = mprj_stimulus
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(MGMT_SOC_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) -I $(MGMT_SOC_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index 7d2c29a..65633bc 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -16,7 +16,7 @@
*/
// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
+#include <defs.h>
// --------------------------------------------------------
@@ -34,7 +34,9 @@
uint32_t testval;
- reg_hkspi_disable = 1; // Shut off the housekeeping SPI,
+ reg_spi_enable = 0;
+
+ // reg_spimaster_cs = 0x00000000; // Shut off the housekeeping SPI,
// so we can use the pins.
reg_mprj_datal = 0x00000000;
@@ -94,10 +96,10 @@
// Configure LA probes [31:0], [127:64] as inputs to the cpu
// Configure LA probes [63:32] as outputs from the cpu
- reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
// Flag start of the test
reg_mprj_datal = 0xAB400000;
@@ -106,7 +108,7 @@
reg_la1_data = 0x00000000;
// Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;
+ reg_la1_oenb = reg_la1_iena = 0x00000000;
reg_mprj_datal = 0xAB410000;
reg_mprj_datah = 0x00000000;
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 0ac0b42..1f956a3 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -17,10 +17,10 @@
`timescale 1 ns / 1 ps
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "tbuart.v"
+// `include "uprj_netlists.v"
+// `include "caravel_netlists.v"
+// `include "spiflash.v"
+// `include "tbuart.v"
module mprj_stimulus_tb;
// Signals declaration
@@ -38,6 +38,7 @@
assign checkbits = mprj_io[31:16];
assign status = mprj_io[35:32];
+
// Force CSB high until simulation is underway
// Note: The CSB GPIO pin default needs to be set to a pull-up. . .
assign mprj_io[3] = CSB;
@@ -53,7 +54,7 @@
$dumpvars(0, mprj_stimulus_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (150) begin
+ repeat (70) begin
repeat (1000) @(posedge clock);
end
$display("%c[1;31m",27);
@@ -67,15 +68,14 @@
$display("Monitor: mprj_stimulus test started");
wait(status == 4'ha);
wait(status == 4'h5);
-
+
// Values reflect copying user-controlled outputs to memory and back
// to management-controlled outputs. Note that there is a slight
// discrepancy in timing when using gate level simulation; either
// of the specified values is okay.
- wait(checkbits == 16'h0840 || checkbits == 16'h0841);
- wait(checkbits == 16'h0a00 || checkbits == 16'h0a01);
-
+ wait(checkbits == 16'h198F);
+ wait(checkbits == 16'h1DDC);
wait(checkbits == 16'hAB51);
$display("Monitor: mprj_stimulus test Passed");
#10000;
@@ -85,11 +85,10 @@
// Reset Operation
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1;
+ CSB <= 1'b1;
+ #1000;
+ RSTB <= 1'b1; // Release reset
#2000;
- RSTB <= 1'b1; // Release reset
- #200000;
- CSB <= 1'bz; // Stop driving CSB
end
initial begin // Power-up sequence
@@ -111,28 +110,32 @@
wire VSS = 1'b0;
caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
);
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 1c784c6..3fd0b56 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -14,83 +14,19 @@
#
# SPDX-License-Identifier: Apache-2.0
-## PDK
-PDK_PATH = $(PDK_ROOT)/sky130A
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../
+# ---- Include Partitioned Makefiles ----
-## RISCV GCC
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
+CONFIG = caravel_user_project
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
-SIM?=RTL
-.SUFFIXES:
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
-PATTERN = wb_port
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-ifeq ($(SIM),RTL)
- iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
- $< -o $@
-else
- iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
- -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
- $< -o $@
-endif
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env
- ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-check-env:
-ifndef PDK_ROOT
- $(error PDK_ROOT is undefined, please export it before running make)
-endif
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
- $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
-endif
-ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
- $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-endif
-# check for efabless style installation
-ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
-SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
-endif
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 425c115..4f59055 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -16,16 +16,14 @@
*/
// This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
/*
Wishbone Test:
- Configures MPRJ lower 8-IO pins as outputs
- Checks counter value through the wishbone port
*/
-int i = 0;
-int clk = 0;
void main()
{
@@ -47,7 +45,9 @@
/* Set up the housekeeping SPI to be connected internally so */
/* that external pin changes don't affect it. */
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ reg_spi_enable = 1;
+ reg_wb_enable = 1;
+ // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
// Connect the housekeeping SPI to the SPI master
@@ -75,15 +75,13 @@
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
- reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
// Flag start of the test
reg_mprj_datal = 0xAB600000;
reg_mprj_slave = 0x00002710;
- if (reg_mprj_slave == 0x2752) {
+ if (reg_mprj_slave == 0x2B3D) {
reg_mprj_datal = 0xAB610000;
- } else {
- reg_mprj_datal = 0xAB600000;
}
}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index b32f900..60529dc 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -17,9 +17,9 @@
`timescale 1 ns / 1 ps
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
+// `include "uprj_netlists.v"
+// `include "caravel_netlists.v"
+// `include "spiflash.v"
module wb_port_tb;
reg clock;
@@ -35,7 +35,7 @@
assign checkbits = mprj_io[31:16];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ // assign mprj_io[3] = CSB;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -52,7 +52,7 @@
$dumpvars(0, wb_port_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (30) begin
+ repeat (50) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
@@ -67,9 +67,9 @@
end
initial begin
- wait(checkbits == 16'h AB60);
+ wait(checkbits == 16'hAB60);
$display("Monitor: MPRJ-Logic WB Started");
- wait(checkbits == 16'h AB61);
+ wait(checkbits == 16'hAB61);
`ifdef GL
$display("Monitor: Mega-Project WB (GL) Passed");
`else
@@ -90,20 +90,10 @@
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
- power3 <= 1'b0;
- power4 <= 1'b0;
- #100;
+ #200;
power1 <= 1'b1;
- #100;
+ #200;
power2 <= 1'b1;
- #100;
- power3 <= 1'b1;
- #100;
- power4 <= 1'b1;
- end
-
- always @(mprj_io) begin
- #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
end
wire flash_csb;
@@ -119,22 +109,26 @@
caravel uut (
.vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
.vssio (VSS),
+ .vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
- .vdda1 (USER_VDD3V3),
- .vdda2 (USER_VDD3V3),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
.vssa1 (VSS),
+ .vssa1_2 (VSS),
.vssa2 (VSS),
- .vccd1 (USER_VDD1V8),
- .vccd2 (USER_VDD1V8),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
- .clock (clock),
+ .clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
