removing old test
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile deleted file mode 100644 index 3fd0b56..0000000 --- a/verilog/dv/wb_port/Makefile +++ /dev/null
@@ -1,32 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - - - -PWDD := $(shell pwd) -BLOCKS := $(shell basename $(PWDD)) - -# ---- Include Partitioned Makefiles ---- - -CONFIG = caravel_user_project - - -include $(MCW_ROOT)/verilog/dv/make/env.makefile -include $(MCW_ROOT)/verilog/dv/make/var.makefile -include $(MCW_ROOT)/verilog/dv/make/cpu.makefile -include $(MCW_ROOT)/verilog/dv/make/sim.makefile - -
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c deleted file mode 100644 index 4f59055..0000000 --- a/verilog/dv/wb_port/wb_port.c +++ /dev/null
@@ -1,87 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020 Efabless Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * SPDX-License-Identifier: Apache-2.0 - */ - -// This include is relative to $CARAVEL_PATH (see Makefile) -#include <defs.h> -#include <stub.c> - -/* - Wishbone Test: - - Configures MPRJ lower 8-IO pins as outputs - - Checks counter value through the wishbone port -*/ - -void main() -{ - - /* - IO Control Registers - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | - Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | - - - Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL - | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | - | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - */ - - /* Set up the housekeeping SPI to be connected internally so */ - /* that external pin changes don't affect it. */ - - reg_spi_enable = 1; - reg_wb_enable = 1; - // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Connect the housekeeping SPI to the SPI master - // so that the CSB line is not left floating. This allows - // all of the GPIO pins to be used for user functions. - - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - - /* Apply configuration */ - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64] - - // Flag start of the test - reg_mprj_datal = 0xAB600000; - - reg_mprj_slave = 0x00002710; - if (reg_mprj_slave == 0x2B3D) { - reg_mprj_datal = 0xAB610000; - } -}
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v deleted file mode 100644 index d5c2983..0000000 --- a/verilog/dv/wb_port/wb_port_tb.v +++ /dev/null
@@ -1,147 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none - -`timescale 1 ns / 1 ps - -module wb_port_tb; - reg clock; - reg RSTB; - reg CSB; - reg power1, power2; - reg power3, power4; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - wire [15:0] checkbits; - - assign checkbits = mprj_io[31:16]; - - assign mprj_io[3] = 1'b1; - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - end - - initial begin - $dumpfile("wb_port.vcd"); - $dumpvars(0, wb_port_tb); - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (70) begin - repeat (1000) @(posedge clock); - // $display("+1000 cycles"); - end - $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed"); - `else - $display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed"); - `endif - $display("%c[0m",27); - $finish; - end - - initial begin - wait(checkbits == 16'hAB60); - $display("Monitor: MPRJ-Logic WB Started"); - wait(checkbits == 16'hAB61); - `ifdef GL - $display("Monitor: Mega-Project WB (GL) Passed"); - `else - $display("Monitor: Mega-Project WB (RTL) Passed"); - `endif - $finish; - end - - initial begin - RSTB <= 1'b0; - CSB <= 1'b1; // Force CSB high - #2000; - RSTB <= 1'b1; // Release reset - #100000; - CSB = 1'b0; // CSB can be released - end - - initial begin // Power-up sequence - power1 <= 1'b0; - power2 <= 1'b0; - #200; - power1 <= 1'b1; - #200; - power2 <= 1'b1; - end - - wire flash_csb; - wire flash_clk; - wire flash_io0; - wire flash_io1; - - wire VDD3V3 = power1; - wire VDD1V8 = power2; - wire USER_VDD3V3 = power3; - wire USER_VDD1V8 = power4; - wire VSS = 1'b0; - - caravel uut ( - .vddio (VDD3V3), - .vddio_2 (VDD3V3), - .vssio (VSS), - .vssio_2 (VSS), - .vdda (VDD3V3), - .vssa (VSS), - .vccd (VDD1V8), - .vssd (VSS), - .vdda1 (VDD3V3), - .vdda1_2 (VDD3V3), - .vdda2 (VDD3V3), - .vssa1 (VSS), - .vssa1_2 (VSS), - .vssa2 (VSS), - .vccd1 (VDD1V8), - .vccd2 (VDD1V8), - .vssd1 (VSS), - .vssd2 (VSS), - .clock (clock), - .gpio (gpio), - .mprj_io (mprj_io), - .flash_csb(flash_csb), - .flash_clk(flash_clk), - .flash_io0(flash_io0), - .flash_io1(flash_io1), - .resetb (RSTB) - ); - - spiflash #( - .FILENAME("wb_port.hex") - ) spiflash ( - .csb(flash_csb), - .clk(flash_clk), - .io0(flash_io0), - .io1(flash_io1), - .io2(), // not used - .io3() // not used - ); - -endmodule -`default_nettype wire \ No newline at end of file