| commit | 8c3175a027351b1659c806628dd02f02effdc44d | [log] [tgz] |
|---|---|---|
| author | Matt Venn <matt@mattvenn.net> | Wed Mar 16 20:40:01 2022 +0100 |
| committer | Matt Venn <matt@mattvenn.net> | Wed Mar 16 20:40:01 2022 +0100 |
| tree | 6b21ae9a320ff92786400052e52ad0ddcea6a34c | |
| parent | f6a9355cc942f6b1a4a128a2f607b50f5320b66f [diff] |
added rgb mixer, freq count, vga clock
This ASIC was designed by members of the Zero to ASIC course.
This submission was configured and built by the multi project tools
# clone all repos, and include support for shared OpenRAM ./multi_tool.py --clone-repos --clone-shared-repos --create-openlane-config --copy-gds --copy-project --openram # run all the tests ./multi_tool.py --test-all --force-delete # build user project wrapper submission cd $CARAVEL_ROOT; make user_project_wrapper # create docs ./multi_tool.py --generate-doc --annotate-image
