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README.md

Zero to ASIC Group submission MPW5

This ASIC was designed by members of the Zero to ASIC course.

This submission was configured and built by the multi project tools at commit bbf3d4692bc84d2b9d88e73f2f29736400eac86a.

# clone all repos, and include support for shared OpenRAM
./multi_tool.py --clone-repos --clone-shared-repos --create-openlane-config --copy-gds --copy-project --openram

# run all the tests
./multi_tool.py --test-all --force-delete

# build user project wrapper submission
cd $CARAVEL_ROOT; make user_project_wrapper

# create docs
./multi_tool.py --generate-doc --annotate-image

multi macro

Project Index

Function generator

Function generator

VGA Clock

VGA Clock

Frequency counter

Frequency counter

RGB Mixer

RGB Mixer

Hack soc

Hack soc

teras

  • Author: Louis Ledoux AKA Binaryman
  • Github: https://github.com/Bynaryman/wrapped_teras
  • commit: 766588bd8519682347ea15680258cd97004fc377
  • Description: matrix multiply unit with exact accumulators, no intermediate roundings, fused-dot-products, and posit arithmetic

teras

ALU74181