Update user_proj_example.v

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index ba52580..115f798 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -43,13 +43,15 @@
     
         input clk,reset,trace_ready,
 	input [31:0] mem_addr, 
-        output [19:0] L1_hit_count,L2_hit_count4,L2_hit_count8,L2_hit_count16,L2_ss1_count4,L2_ss1_count8,L2_ss1_count16,L2_ss2_count4,L2_ss2_count8,L2_ss2_count16
+        output [19:0] L1_hit_count,L2_hit_count4,L2_hit_count8,L2_hit_count16,L2_ss1_count4,L2_ss1_count8,L2_ss1_count16,L2_ss2_count4,L2_ss2_count8,L2_ss2_count16,
+	output updated
 );   
     	main cache (
 	    .clk(clk), 
 	    .reset(reset),
 	    .trace_ready(trace_ready),
 	    .mem_addr(mem_addr),
+	    .updated(updated),
 	    .L1_hit_count(L1_hit_count),
 	    .L2_hit_count4(L2_hit_count4),
 	    .L2_hit_count8(L2_hit_count8),