commit 7bd5b16a83323a7d04b94dd023c8793c0eecccd0
author Shivani Shah <shivani.shah269@gmail.com> Sun Mar 20 18:11:52 2022 +0530
committer GitHub <noreply@github.com> Sun Mar 20 18:11:52 2022 +0530
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README.md

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 # Cache Simulator
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+[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
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 Computer architects need to choose the design configurations which will work effectively across most commonly used workloads. Our work enables the architect to choose the right configuration based on metrics such as hit rates, power, area, and timing. We implement an FPGA accelerated parameterized two-level multi-core cache simulator called Cache-accel which can be partially reconfigured to include prefetching. The key motivation behind the idea is the speed with which the design space exploration can be carried out by exploiting the parallelism available in an FPGA and the accuracy of the results as compared to a software simulator.
 
 You can find more details about our project over here: [FPGA Accelerated Multi-Core Cache Simulator](https://github.com/shivanishah269/FPGA_based_Multicore_Cache_Simuator)