commit 71db7ecd2aa757c8492c7b5e7df483627e5f6f42
author Shivani Shah <shivani.shah269@gmail.com> Thu Dec 23 13:25:45 2021 +0530
committer GitHub <noreply@github.com> Thu Dec 23 13:25:45 2021 +0530
tree 5be95ef9a3b5a7c967978e820bf8d16374e008f3
parent 26c669f6a0feb6d403379aef78d513e1c7419fad

Update main.v

verilog/rtl/main.v

diff --git a/verilog/rtl/main.v b/verilog/rtl/main.v
index 046d099..372dc0d 100644
--- a/verilog/rtl/main.v
+++ b/verilog/rtl/main.v
@@ -1,4 +1,4 @@
-module main(clk,reset,trace_ready,mem_addr,L1_hit_count,L2_hit_count4,L2_hit_count8,L2_hit_count16,L2_ss1_count4,L2_ss1_count8,L2_ss1_count16,L2_ss2_count4,L2_ss2_count8,L2_ss2_count16);
+module main(clk,reset,trace_ready,mem_addr,updated,L1_hit_count,L2_hit_count4,L2_hit_count8,L2_hit_count16,L2_ss1_count4,L2_ss1_count8,L2_ss1_count16,L2_ss2_count4,L2_ss2_count8,L2_ss2_count16);
 
     parameter L1_way = 4;
     parameter L1_block_size_byte = 16;
@@ -21,7 +21,7 @@
     input [31:0] mem_addr;
     
     output [19:0] L1_hit_count,L2_hit_count4,L2_hit_count8,L2_hit_count16,L2_ss1_count4,L2_ss1_count8,L2_ss1_count16,L2_ss2_count4,L2_ss2_count8,L2_ss2_count16;
-    wire updated;    
+    output updated;    
     
     // variables to divide address in tag, index and offset for L1 cache
     wire [31-L1_set_index-L1_block_offset_index:0] L1_tag;