Update user_proj_example.v
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 9504256..ba52580 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -41,10 +41,10 @@
inout vssd1, // User area 1 digital ground
`endif
- input clk,reset,trace_ready;
- input [31:0] mem_addr;
- output [19:0] L1_hit_count,L2_hit_count4,L2_hit_count8,L2_hit_count16,L2_ss1_count4,L2_ss1_count8,L2_ss1_count16,L2_ss2_count4,L2_ss2_count8,L2_ss2_count16;
-
+ input clk,reset,trace_ready,
+ input [31:0] mem_addr,
+ output [19:0] L1_hit_count,L2_hit_count4,L2_hit_count8,L2_hit_count16,L2_ss1_count4,L2_ss1_count8,L2_ss1_count16,L2_ss2_count4,L2_ss2_count8,L2_ss2_count16
+);
main cache (
.clk(clk),
.reset(reset),
@@ -63,3 +63,5 @@
);
endmodule
+
+`default_nettype wire
