| commit | f2d12068e0a0ea12723d7a7859622cbf10f01811 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Sat Apr 30 16:22:07 2022 -0700 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Sat Apr 30 16:22:07 2022 -0700 |
| tree | 4f038f19986ee2a4a2739e9be5063111569c260c | |
| parent | 0f7c70af5d080fd167a023554533459d380176cb [diff] |
final gds oasis
PLL-BASED CAPACITIVE SENSOR INTERFACE
This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:
The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
The characteristic plot for an average window of 10us is seen below:
Refer to README for this sample project documentation.
