| commit | e7f1e4ec5e1cb3f5a2d8109dc285d165b248bae0 | [log] [tgz] |
|---|---|---|
| author | Jorge Marin <jorge.marin.ndez@gmail.com> | Mon Mar 21 21:23:32 2022 -0300 |
| committer | Jorge Marin <jorge.marin.ndez@gmail.com> | Mon Mar 21 21:23:32 2022 -0300 |
| tree | 60185cd1daaefc87ba828c91e916ceb5e69785bc | |
| parent | 0e4536a6b8e0622d3e1ff33060f20dc5c9aee193 [diff] |
MPW5, back to orig ok
PLL-BASED CAPACITIVE SENSOR INTERFACE
This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:
The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
The characteristic plot for an average window of 10us is seen below:
Refer to README for this sample project documentation.