Redid the layout for the example analog project based on the updated
wrapper layout. Generated GDS and extracted netlist.
diff --git a/netgen/run_wrapper.sh b/netgen/run_wrapper.sh
new file mode 100755
index 0000000..d84d94f
--- /dev/null
+++ b/netgen/run_wrapper.sh
@@ -0,0 +1,22 @@
+#!/bin/sh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+#--------------------------------------------------------------------------------
+# Run LVS on the user_analog_project_wrapper layout, comparing against the
+# top-level verilog module
+#
+#--------------------------------------------------------------------------------
+netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "../verilog/rtl/user_analog_proj_example.v user_analog_proj_example" /usr/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl comp.out
