| commit | d048b0a566696f77069dc9644ddabee103141114 | [log] [tgz] |
|---|---|---|
| author | Jorge Marin <jorge.marin.ndez@gmail.com> | Sun Jan 09 00:06:14 2022 -0300 |
| committer | Jorge Marin <jorge.marin.ndez@gmail.com> | Sun Jan 09 00:06:14 2022 -0300 |
| tree | 9c819fdf98c7096ff2ff95ce862b526c7e260dbd | |
| parent | b8d4297fbfd0593101db3d0bd8fc2680b12cd2f3 [diff] |
Full top cell connection to wrapper upload, DRC and netgen .spice uncommented
PLL-BASED CAPACITIVE SENSOR INTERFACE
This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:
The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
The characteristic plot for an average window of 10us is seen below:
Refer to README for this sample project documentation.