commit 5e086e86a9b5ab1bb2d070a8b62e4e76046871dd
author JorgeMarinN <93881221+JorgeMarinN@users.noreply.github.com> Fri Dec 31 13:38:29 2021 -0300
committer GitHub <noreply@github.com> Fri Dec 31 13:38:29 2021 -0300
tree 7c4b83afc616e57cc43228c84cb375d4a3af3865
parent 70cb904a9a70536816314c11156d19a207952b95

Update README.md

README.md

diff --git a/README.md b/README.md
index 80a6cd8..8fe1874 100644
--- a/README.md
+++ b/README.md
@@ -9,9 +9,14 @@
 
 ![image](https://user-images.githubusercontent.com/93881221/147831652-41cf39a6-2140-4b39-a2b3-ab59a673443d.png)
 
-The architecture has been tested for a DC sweep of input capacitive values. The characteristic plot for an average window of 10us is seen below:
+The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
 
-![image](https://user-images.githubusercontent.com/93881221/147832157-99f9d210-2572-4856-a674-c2a69fd72ddf.png)
+![image](https://user-images.githubusercontent.com/93881221/147832655-a40a443d-7c19-4a10-b0fd-b3201bb741cb.png)
+
+The characteristic plot for an average window of 10us is seen below:
+
+![image](https://user-images.githubusercontent.com/93881221/147832381-bbd27e83-ee83-4d5a-b145-8559156f3f49.png)
+