| commit | 5e086e86a9b5ab1bb2d070a8b62e4e76046871dd | [log] [tgz] |
|---|---|---|
| author | JorgeMarinN <93881221+JorgeMarinN@users.noreply.github.com> | Fri Dec 31 13:38:29 2021 -0300 |
| committer | GitHub <noreply@github.com> | Fri Dec 31 13:38:29 2021 -0300 |
| tree | 7c4b83afc616e57cc43228c84cb375d4a3af3865 | |
| parent | 70cb904a9a70536816314c11156d19a207952b95 [diff] |
Update README.md
PLL-BASED CAPACITIVE SENSOR INTERFACE
This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:
The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
The characteristic plot for an average window of 10us is seen below:
Refer to README for this sample project documentation.