| commit | e441a7e1d7b3ff1a011fe334f6a1aec1ebc5a75b | [log] [tgz] |
|---|---|---|
| author | Jorge Marin <jorge.marin.ndez@gmail.com> | Mon Mar 21 22:12:49 2022 -0300 |
| committer | Jorge Marin <jorge.marin.ndez@gmail.com> | Mon Mar 21 22:12:49 2022 -0300 |
| tree | f9213b0ccbca2f82b78c60e863c419b9c0a43681 | |
| parent | dced61451a091fff807b7f201baf472fe4483e5f [diff] |
MPW5, bigger polygons 2
PLL-BASED CAPACITIVE SENSOR INTERFACE
This project involves the design of a capacitive sensor-to-digital converter using time-based circuit techniques. It uses basic digitally-oriented building blocks (two oscillators, a D-flipflop and a feedback loop including a capacitive element and a switch) to convert input capacitive values into digital single bit traces in the time domain. The basic block diagram can be seen below:
The architecture has been tested for a DC sweep of input capacitive values. Example output trace values for different capacitance inputs are shown below:
The characteristic plot for an average window of 10us is seen below:
Refer to README for this sample project documentation.