commit: 6e0fb962c936fb56c74b371b7da06fcd287bbca1
[log] [tgz]
author: Staf Verhaegen <staf@fibraservi.eu>
Thu Dec 30 10:50:09 2021 +0100
committer: Staf Verhaegen <staf@fibraservi.eu>
Thu Dec 30 10:50:09 2021 +0100
tree: 145b64649da8eeab48b85974a6ad05ff99cadfe0
parent: 12d70c9cd2dcba55ede06668f13f30963af04d1d [diff]

First connected out version

* Add logic inside IORO signal to enable and drive output of RO.
* Connected input/outputs of instantiated subcells to pins on the top cell.

doitcode/frame.py[diff]
doitcode/generate.py[diff]
gds/user_analog_project_wrapper.gds.gz[diff]

3 files changed

tree: 145b64649da8eeab48b85974a6ad05ff99cadfe0

.github/
docs/
doitcode/
gds/
mag/
netgen/
openlane/
verilog/
xschem/
caravel
.gitignore
.gitlab-ci.yml
dodo.py
LICENSE
Makefile
README.md

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.