Updated the layout to properly use the metal resistors in front of
pins that are connected to the same net.  Updated the GDS with this
change, and also to properly generate hierarchical layers, which
apparently had not been done previously.  Verilog and schematic
have not yet been updated with the metal resistor change, and so
will fail LVS until they are.
3 files changed
tree: 76d81ffcbd54654fb9857c795d14849d62e8d675
  1. .github/
  2. docs/
  3. gds/
  4. mag/
  5. netgen/
  6. openlane/
  7. verilog/
  8. xschem/
  9. .gitignore
  11. Makefile
  12. README.md

Caravel Analog User

License CI Caravan Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:Use this sample project for analog user projects.

Refer to README for this sample project documentation.