| commit | 2568028f73ea84c5e238014e6cfb888e2e78d43a | [log] [tgz] |
|---|---|---|
| author | Egor Lukyanchenko <egor@bush.lan> | Thu Dec 30 17:10:52 2021 +0300 |
| committer | Egor Lukyanchenko <egor@bush.lan> | Thu Dec 30 17:10:52 2021 +0300 |
| tree | c7d13b37f2f771a65236b532479f45335f5600bd | |
| parent | f023eb1910a02766dbf028ed56bbedcb12c15858 [diff] |
Fix power ports in netlist
Ariel is a test project implementing open-source Uranus eFPGA fabric for OpenMPW-4 using open source Skywater PDK and OpenLane flow. FPGA contains 880 4-input LUTs and uses Wishbone bus from Caravel test harness for bitstream loading and user projects.
Project is implemented for Skywater 130nm ASIC technology using slightly modified OpenLane open source flow. Synthesis is done in two steps: first Yosys+GHDL are used for VHDL to Verilog translation, and then resulting Verilog source is synthesized by Yosys inside OpenLane flow.
Uranus FPGA uses opensource flow for FPGA bitstream generation. Yosys (with optional GHDL frontend for VHDL) is used for synthesis and VPR for place and route. Flow glue and bitstream generation is done by custom Python scripts.
This repository contains mainly implementation products (GDS/netlists/etc) needed for OpenMPW and test Caravel programs. VHDL sources of Uranus FPGA fabric, FPGA flow, tests and simulation scripts will be released later in separate repository.
DOCUMENTATION UNDER DEVELOPMENT