)]}'
{
  "commit": "2568028f73ea84c5e238014e6cfb888e2e78d43a",
  "tree": "c7d13b37f2f771a65236b532479f45335f5600bd",
  "parents": [
    "f023eb1910a02766dbf028ed56bbedcb12c15858"
  ],
  "author": {
    "name": "Egor Lukyanchenko",
    "email": "egor@bush.lan",
    "time": "Thu Dec 30 17:10:52 2021 +0300"
  },
  "committer": {
    "name": "Egor Lukyanchenko",
    "email": "egor@bush.lan",
    "time": "Thu Dec 30 17:10:52 2021 +0300"
  },
  "message": "Fix power ports in netlist\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ecf838386fb3bb33c4f20b6d629609219a8254ac",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v.gz",
      "new_id": "4b8f3493276cf1db80af23494aa43584256eaa44",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_wrapper.v.gz"
    }
  ]
}