blob: 7b9b5304288dcbaf0bba49dc4481e1662694a126 [file] [log] [blame]
---
project:
description: "System on a Chip built around a RISC-V based 5 stage pipelined core Buraq-Mini."
foundry: "SkyWater"
git_url: "https://github.com/hadirkhan10/caravel_ibtida_soc.git"
organization: "Micro-Electronics Research Laboratory"
organization_url: "https://merledupk.org"
owner: "Hadir Khan"
process: "SKY130"
project_name: "Ibtida-II"
tags:
- "Open MPW"
- "Chisel"
category: "processor"
top_level_netlist: "verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "1.00"
cover_image: "doc/ibtida-logo.png"