add dv test exercising wishbone and sram
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index d87238f..9483154 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus +PATTERNS = wb_leds all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/wb_leds/Makefile b/verilog/dv/wb_leds/Makefile new file mode 100644 index 0000000..cc00101 --- /dev/null +++ b/verilog/dv/wb_leds/Makefile
@@ -0,0 +1,79 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +## Caravel Pointers +CARAVEL_ROOT ?= ../../../caravel +CARAVEL_PATH ?= $(CARAVEL_ROOT) +CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel +CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog +CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl +CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel + +## User Project Pointers +UPRJ_VERILOG_PATH ?= ../../../verilog +UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl +UPRJ_BEHAVIOURAL_MODELS = ../ + +## RISCV GCC +PDK_ROOT?=/local/home/roman/projects/opencircuitdesign/shuttle4/pdks +GCC_PATH?=/opt/xpack-riscv-none-embed-gcc/bin +GCC_PREFIX?=riscv-none-embed +PDK_PATH?=$(PDK_ROOT)/sky130A + +## Simulation mode: RTL/GL +SIM?=RTL + +.SUFFIXES: + +PATTERN = wb_leds + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex +ifeq ($(SIM),RTL) + iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_RTL_PATH) -I ../../../openlane/user_proj/src \ + $< -o $@ +else + iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ + $< -o $@ +endif + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s + ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all
diff --git a/verilog/dv/wb_leds/wb_leds.c b/verilog/dv/wb_leds/wb_leds.c new file mode 100644 index 0000000..e229962 --- /dev/null +++ b/verilog/dv/wb_leds/wb_leds.c
@@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include "verilog/dv/caravel/defs.h" +#include "verilog/dv/caravel/stub.c" + +/* + Wishbone Test: + - Configures MPRJ lower 8-IO pins as outputs + - Checks led value through the wishbone port +*/ + +#define reg_wb_leds (*(volatile uint32_t*)0x30fffd00) +#define reg_sram (*(volatile uint32_t*)0x30000000) +#define reg_sram1 (*(volatile uint32_t*)0x30001000) + +void main() +{ + + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + + reg_spimaster_config = 0xa002; // Enable, prescaler = 2, + // connect to housekeeping SPI + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;//led + reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;//trstb + //reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_PULLDOWN;//srstb + + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + //reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] + + // Flag start of the test + reg_mprj_datal = 0x00060000; + + // set the led, signalling the end of the test + reg_wb_leds = 0xff; + reg_sram = 0x01234567; + reg_sram1 = 0xdeadbeef; + + if (reg_wb_leds == 0xff && reg_sram == 0x01234567 && reg_sram1 == 0xdeadbeef) { + reg_mprj_datal = 0x00070000; + } else { + reg_mprj_datal = 0x00060000; + } +}
diff --git a/verilog/dv/wb_leds/wb_leds.gtkw b/verilog/dv/wb_leds/wb_leds.gtkw new file mode 100644 index 0000000..d867db7 --- /dev/null +++ b/verilog/dv/wb_leds/wb_leds.gtkw
@@ -0,0 +1,170 @@ +[*] +[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI +[*] Wed Dec 29 05:13:16 2021 +[*] +[dumpfile] "/local/home/roman/projects/opencircuitdesign/shuttle4/caravel_user_project/verilog/dv/wb_leds/wb_leds.vcd" +[dumpfile_mtime] "Wed Dec 29 05:05:55 2021" +[dumpfile_size] 174507059 +[savefile] "/local/home/roman/projects/opencircuitdesign/shuttle4/caravel_user_project/verilog/dv/wb_leds/wb_leds.gtkw" +[timestart] 0 +[size] 3092 1672 +[pos] -1 -1 +*-24.365459 152937500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] wb_leds_tb. +[treeopen] wb_leds_tb.uut. +[treeopen] wb_leds_tb.uut.mprj. +[treeopen] wb_leds_tb.uut.mprj.mprj. +[treeopen] wb_leds_tb.uut.mprj.mprj.soc. +[treeopen] wb_leds_tb.uut.mprj.mprj.soc.cpu0. +[treeopen] wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0. +[sst_width] 605 +[signals_width] 702 +[sst_expanded] 1 +[sst_vpaned_height] 864 +@200 +-qspi +@28 +wb_leds_tb.spiflash.clk +wb_leds_tb.spiflash.csb +@22 +wb_leds_tb.spiflash.spi_addr[23:0] +@200 +-uut +@28 +wb_leds_tb.uut.caravel_clk +wb_leds_tb.uut.caravel_clk2 +wb_leds_tb.uut.caravel_rstn +wb_leds_tb.uut.clock +wb_leds_tb.uut.resetb +wb_leds_tb.uut.clock_core +wb_leds_tb.uut.mprj_clock +wb_leds_tb.uut.mprj_clock2 +wb_leds_tb.uut.mprj_reset +@200 +-mprj +@28 +wb_leds_tb.uut.mprj.user_clock2 +wb_leds_tb.uut.mprj.wb_clk_i +wb_leds_tb.uut.mprj.wb_rst_i +@22 +wb_leds_tb.uut.mprj.wbs_adr_i[31:0] +wb_leds_tb.uut.mprj.wbs_dat_i[31:0] +wb_leds_tb.uut.mprj.wbs_dat_o[31:0] +@28 +wb_leds_tb.uut.mprj.wbs_stb_i +wb_leds_tb.uut.mprj.wbs_cyc_i +wb_leds_tb.uut.mprj.wbs_ack_o +@22 +wb_leds_tb.uut.mprj.wbs_sel_i[3:0] +@28 +wb_leds_tb.uut.mprj.wbs_we_i +@200 +- +@28 +wb_leds_tb.uut.mprj.mprj.clk_i +wb_leds_tb.uut.mprj.mprj.rst_i +wb_leds_tb.uut.mprj.mprj.wb_clk_i +wb_leds_tb.uut.mprj.mprj.wb_rst_i +@22 +wb_leds_tb.uut.mprj.mprj.wbs_adr_i[31:0] +wb_leds_tb.uut.mprj.mprj.wbs_dat_i[31:0] +wb_leds_tb.uut.mprj.mprj.wbs_dat_o[31:0] +@200 +-soc +@28 +wb_leds_tb.uut.mprj.mprj.soc.clk +wb_leds_tb.uut.mprj.mprj.soc.rst +wb_leds_tb.uut.mprj.mprj.soc.jtag_tck +wb_leds_tb.uut.mprj.mprj.soc.jtag_trst +wb_leds_tb.uut.mprj.mprj.soc.LED +wb_leds_tb.uut.mprj.mprj.soc.wb_clk +wb_leds_tb.uut.mprj.mprj.soc.wb_rst +@22 +wb_leds_tb.uut.mprj.mprj.soc.mprj_dat_i[31:0] +wb_leds_tb.uut.mprj.mprj.soc.mprj_dat_o[31:0] +@200 +-cpu +@28 +wb_leds_tb.uut.mprj.mprj.soc.cpu0.clk +wb_leds_tb.uut.mprj.mprj.soc.cpu0.reset +wb_leds_tb.uut.mprj.mprj.soc.cpu0.jtag_tck +wb_leds_tb.uut.mprj.mprj.soc.cpu0.jtag_rst +@22 +wb_leds_tb.uut.mprj.mprj.soc.cpu0.memory_PC[31:0] +@200 +-led +@28 +wb_leds_tb.uut.mprj.mprj.soc.led.i_clk +wb_leds_tb.uut.mprj.mprj.soc.led.i_reset +wb_leds_tb.uut.mprj.mprj.soc.led.register_index +@22 +wb_leds_tb.uut.mprj.mprj.soc.led.i_wb_adr[31:0] +wb_leds_tb.uut.mprj.mprj.soc.led.i_wb_dat[31:0] +@29 +wb_leds_tb.uut.mprj.mprj.soc.led.o_led +@28 +wb_leds_tb.uut.mprj.mprj.soc.led.o_wb_ack +@22 +wb_leds_tb.uut.mprj.mprj.soc.led.o_wb_dat[31:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.led.i_wb_stb +wb_leds_tb.uut.mprj.mprj.soc.led.i_wb_we +@22 +wb_leds_tb.uut.mprj.mprj.soc.led.i_wb_sel[3:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.led.i_wb_cyc +@200 +-interconnect +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_clk_i +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_rst_i +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_ack_o +@22 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_adr_i[31:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_bte_i[1:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_cti_i[2:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_cyc_i +@22 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_dat_i[31:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_dat_o[31:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_err_o +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_rty_o +@22 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_sel_i[3:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_stb_i +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_mgmt_we_i +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_ack_i +@22 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_adr_o[31:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_bte_o[1:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_cti_o[2:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_cyc_o +@22 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_dat_i[31:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_dat_o[31:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_err_i +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_rty_i +@22 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_sel_o[3:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_stb_o +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_led0_we_o +@22 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_m2s_mgmt_cpu0_rom_adr[31:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_m2s_mgmt_cpu0_rom_bte[1:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_m2s_mgmt_cpu0_rom_cti[2:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_m2s_mgmt_cpu0_rom_cyc +@22 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_m2s_mgmt_cpu0_rom_dat[31:0] +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_m2s_mgmt_cpu0_rom_sel[3:0] +@28 +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_m2s_mgmt_cpu0_rom_stb +wb_leds_tb.uut.mprj.mprj.soc.wb_interconA0.wb_m2s_mgmt_cpu0_rom_we +[pattern_trace] 1 +[pattern_trace] 0
diff --git a/verilog/dv/wb_leds/wb_leds_tb.v b/verilog/dv/wb_leds/wb_leds_tb.v new file mode 100644 index 0000000..5526026 --- /dev/null +++ b/verilog/dv/wb_leds/wb_leds_tb.v
@@ -0,0 +1,168 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "uprj_netlists.v" +`include "caravel_netlists.v" +`include "spiflash.v" + +module wb_leds_tb; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire led; + wire [2:0] checkbits; + + assign checkbits = mprj_io[18:16]; + assign led = mprj_io[25]; + +// assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("wb_leds.vcd"); + $dumpvars(0, wb_leds_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (30) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed"); + `else + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + initial begin + wait(checkbits == 3'h 6); + $display("Monitor: checkbits=6"); + + // wait for leds to get set + wait(led == 1'b0); + $display("Monitor: LED=0"); + + wait(led == 1'b1); + $display("Monitor: LED=1"); + + wait(checkbits == 3'h 7); + $display("Monitor: checkbits=7"); + + `ifdef GL + $display("Monitor: Test 1 Mega-Project IO (GL) Passed"); + `else + $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + `endif + $finish; + end + + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #170000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #100; + power1 <= 1'b1; + #100; + power2 <= 1'b1; + #100; + power3 <= 1'b1; + #100; + power4 <= 1'b1; + end + + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + wire VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("wb_leds.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 6e09a5d..17dd6d2 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -33,8 +33,8 @@ `include "../../../openlane/user_proj/src/wb_arbiter.v" `include "../../../openlane/user_proj/src/wb_mux.v" `include "../../../openlane/user_proj/src/wb_interconnect.v" -// `include "../../../openlane/user_proj/src/simpleuart.v" `include "../../../openlane/user_proj/src/wb_openram_wrapper.v" `include "../../../openlane/user_proj/src/wb_led.v" `include "../../../openlane/user_proj/src/timer_wb.v" + `include "../../../openlane/user_proj/src/simpleuart.v" `endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v deleted file mode 100644 index ffde4f1..0000000 --- a/verilog/rtl/user_project_wrapper.v +++ /dev/null
@@ -1,123 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none -/* - *------------------------------------------------------------- - * - * user_project_wrapper - * - * This wrapper enumerates all of the pins available to the - * user for the user project. - * - * An example user project is provided in this wrapper. The - * example should be removed and replaced with the actual - * user project. - * - *------------------------------------------------------------- - */ - -module user_project_wrapper #( - parameter BITS = 32 -) ( -`ifdef USE_POWER_PINS - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground - inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply - inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // Analog (direct connection to GPIO pad---use with caution) - // Note that analog I/O is not available on the 7 lowest-numbered - // GPIO pads, and so the analog_io indexing is offset from the - // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io). - inout [`MPRJ_IO_PADS-10:0] analog_io, - - // Independent clock (on independent integer divider) - input user_clock2, - - // User maskable interrupt signals - output [2:0] user_irq -); - -/*--------------------------------------*/ -/* User project is instantiated here */ -/*--------------------------------------*/ - -user_proj mprj ( -`ifdef USE_POWER_PINS - .vccd1(vccd1), // User area 1 1.8V power - .vssd1(vssd1), // User area 1 digital ground -`endif - - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - - // MGMT SoC Wishbone Slave - - .wbs_cyc_i(wbs_cyc_i), - .wbs_stb_i(wbs_stb_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_adr_i(wbs_adr_i), - .wbs_dat_i(wbs_dat_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), - - // Logic Analyzer - - .la_data_in(la_data_in), - .la_data_out(la_data_out), - .la_oenb (la_oenb), - - // IO Pads - - .io_in (io_in), - .io_out(io_out), - .io_oeb(io_oeb), - - // IRQ - .irq(user_irq) -); - -endmodule // user_project_wrapper - -`default_nettype wire