update dv tests
diff --git a/openlane/user_proj/src/simpleuart.v b/openlane/user_proj/src/simpleuart.v
index 280f9b2..57d4a23 100644
--- a/openlane/user_proj/src/simpleuart.v
+++ b/openlane/user_proj/src/simpleuart.v
@@ -20,8 +20,8 @@
* SPDX-License-Identifier: ISC
*/
-module simpleuart_wb # (
- parameter BASE_ADR = 32'h4000_1000,
+module simpleuartA_wb # (
+ parameter BASE_ADR = 32'h 2000_0000,
parameter CLK_DIV = 8'h00,
parameter DATA = 8'h04,
parameter CONFIG = 8'h08
@@ -44,31 +44,31 @@
input ser_rx
);
- wire [31:0] simpleuart_reg_div_do;
- wire [31:0] simpleuart_reg_dat_do;
- wire [31:0] simpleuart_reg_cfg_do;
+ wire [31:0] simpleuartA_reg_div_do;
+ wire [31:0] simpleuartA_reg_dat_do;
+ wire [31:0] simpleuartA_reg_cfg_do;
wire reg_dat_wait;
wire resetn = ~wb_rst_i;
wire valid = wb_stb_i && wb_cyc_i;
- wire simpleuart_reg_div_sel = valid && (wb_adr_i == (BASE_ADR | CLK_DIV));
- wire simpleuart_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));
- wire simpleuart_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
+ wire simpleuartA_reg_div_sel = valid && (wb_adr_i == (BASE_ADR | CLK_DIV));
+ wire simpleuartA_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));
+ wire simpleuartA_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
- wire [3:0] reg_div_we = simpleuart_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000;
- wire reg_dat_we = simpleuart_reg_dat_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0; // simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0
- wire reg_cfg_we = simpleuart_reg_cfg_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0;
+ wire [3:0] reg_div_we = simpleuartA_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000;
+ wire reg_dat_we = simpleuartA_reg_dat_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0; // simpleuartA_reg_dat_sel ? mem_wstrb[0] : 1'b 0
+ wire reg_cfg_we = simpleuartA_reg_cfg_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0;
wire [31:0] mem_wdata = wb_dat_i;
- wire reg_dat_re = simpleuart_reg_dat_sel && !wb_sel_i && ~wb_we_i; // read_enable
+ wire reg_dat_re = simpleuartA_reg_dat_sel && !wb_sel_i && ~wb_we_i; // read_enable
- assign wb_dat_o = simpleuart_reg_div_sel ? simpleuart_reg_div_do:
- simpleuart_reg_cfg_sel ? simpleuart_reg_cfg_do:
- simpleuart_reg_dat_do;
- assign wb_ack_o = (simpleuart_reg_div_sel || simpleuart_reg_dat_sel
- || simpleuart_reg_cfg_sel) && (!reg_dat_wait);
+ assign wb_dat_o = simpleuartA_reg_div_sel ? simpleuartA_reg_div_do:
+ simpleuartA_reg_cfg_sel ? simpleuartA_reg_cfg_do:
+ simpleuartA_reg_dat_do;
+ assign wb_ack_o = (simpleuartA_reg_div_sel || simpleuartA_reg_dat_sel
+ || simpleuartA_reg_cfg_sel) && (!reg_dat_wait);
- simpleuart simpleuart (
+ simpleuartA simpleuartA (
.clk (wb_clk_i),
.resetn (resetn),
@@ -78,22 +78,22 @@
.reg_div_we (reg_div_we),
.reg_div_di (mem_wdata),
- .reg_div_do (simpleuart_reg_div_do),
+ .reg_div_do (simpleuartA_reg_div_do),
.reg_cfg_we (reg_cfg_we),
.reg_cfg_di (mem_wdata),
- .reg_cfg_do (simpleuart_reg_cfg_do),
+ .reg_cfg_do (simpleuartA_reg_cfg_do),
.reg_dat_we (reg_dat_we),
.reg_dat_re (reg_dat_re),
.reg_dat_di (mem_wdata),
- .reg_dat_do (simpleuart_reg_dat_do),
+ .reg_dat_do (simpleuartA_reg_dat_do),
.reg_dat_wait(reg_dat_wait)
);
endmodule
-module simpleuart (
+module simpleuartA (
input clk,
input resetn,
diff --git a/openlane/user_proj/src/soc.v b/openlane/user_proj/src/soc.v
index c50d0ac..85c53b8 100644
--- a/openlane/user_proj/src/soc.v
+++ b/openlane/user_proj/src/soc.v
@@ -52,214 +52,12 @@
output o_csb1_1
);
-/***************************************************************************/
-// THE BASE ADDRESSES SHOULD MATCH yb_interconnect.yml
+`include "wb_interconnect.vh"
parameter ROM_BASE_ADDRESS = 32'h3000_0000;
-parameter RAM_BASE_ADDRESS = 32'h3000_3000;
-parameter TIMER_BASE_ADDRESS = 32'h4000_0000;
-parameter UART_BASE_ADR = 32'h4000_1000;
-parameter LED_BASE_ADR = 32'h4000_2000;
-//`include "openlane_test/wb_interconnect.vh"
-// THIS FILE IS AUTOGENERATED BY wb_intercon_gen
-// ANY MANUAL CHANGES WILL BE LOST
-wire [31:0] wb_m2s_cpu0_ibus_adr;
-wire [31:0] wb_m2s_cpu0_ibus_dat;
-wire [3:0] wb_m2s_cpu0_ibus_sel;
-wire wb_m2s_cpu0_ibus_we;
-wire wb_m2s_cpu0_ibus_cyc;
-wire wb_m2s_cpu0_ibus_stb;
-wire [2:0] wb_m2s_cpu0_ibus_cti;
-wire [1:0] wb_m2s_cpu0_ibus_bte;
-wire [31:0] wb_s2m_cpu0_ibus_dat;
-wire wb_s2m_cpu0_ibus_ack;
-wire wb_s2m_cpu0_ibus_err;
-wire wb_s2m_cpu0_ibus_rty;
-wire [31:0] wb_m2s_cpu0_dbus_adr;
-wire [31:0] wb_m2s_cpu0_dbus_dat;
-wire [3:0] wb_m2s_cpu0_dbus_sel;
-wire wb_m2s_cpu0_dbus_we;
-wire wb_m2s_cpu0_dbus_cyc;
-wire wb_m2s_cpu0_dbus_stb;
-wire [2:0] wb_m2s_cpu0_dbus_cti;
-wire [1:0] wb_m2s_cpu0_dbus_bte;
-wire [31:0] wb_s2m_cpu0_dbus_dat;
-wire wb_s2m_cpu0_dbus_ack;
-wire wb_s2m_cpu0_dbus_err;
-wire wb_s2m_cpu0_dbus_rty;
-wire [31:0] wb_m2s_mgmt_adr;
-wire [31:0] wb_m2s_mgmt_dat;
-wire [3:0] wb_m2s_mgmt_sel;
-wire wb_m2s_mgmt_we;
-wire wb_m2s_mgmt_cyc;
-wire wb_m2s_mgmt_stb;
-wire [2:0] wb_m2s_mgmt_cti;
-wire [1:0] wb_m2s_mgmt_bte;
-wire [31:0] wb_s2m_mgmt_dat;
-wire wb_s2m_mgmt_ack;
-wire wb_s2m_mgmt_err;
-wire wb_s2m_mgmt_rty;
-wire [31:0] wb_m2s_timer0_adr;
-wire [31:0] wb_m2s_timer0_dat;
-wire [3:0] wb_m2s_timer0_sel;
-wire wb_m2s_timer0_we;
-wire wb_m2s_timer0_cyc;
-wire wb_m2s_timer0_stb;
-wire [2:0] wb_m2s_timer0_cti;
-wire [1:0] wb_m2s_timer0_bte;
-wire [31:0] wb_s2m_timer0_dat;
-wire wb_s2m_timer0_ack;
-wire wb_s2m_timer0_err;
-wire wb_s2m_timer0_rty;
-wire [31:0] wb_m2s_uart0_adr;
-wire [31:0] wb_m2s_uart0_dat;
-wire [3:0] wb_m2s_uart0_sel;
-wire wb_m2s_uart0_we;
-wire wb_m2s_uart0_cyc;
-wire wb_m2s_uart0_stb;
-wire [2:0] wb_m2s_uart0_cti;
-wire [1:0] wb_m2s_uart0_bte;
-wire [31:0] wb_s2m_uart0_dat;
-wire wb_s2m_uart0_ack;
-wire wb_s2m_uart0_err;
-wire wb_s2m_uart0_rty;
-wire [31:0] wb_m2s_led0_adr;
-wire [31:0] wb_m2s_led0_dat;
-wire [3:0] wb_m2s_led0_sel;
-wire wb_m2s_led0_we;
-wire wb_m2s_led0_cyc;
-wire wb_m2s_led0_stb;
-wire [2:0] wb_m2s_led0_cti;
-wire [1:0] wb_m2s_led0_bte;
-wire [31:0] wb_s2m_led0_dat;
-wire wb_s2m_led0_ack;
-wire wb_s2m_led0_err;
-wire wb_s2m_led0_rty;
-wire [31:0] wb_m2s_cpu0_rom_adr;
-wire [31:0] wb_m2s_cpu0_rom_dat;
-wire [3:0] wb_m2s_cpu0_rom_sel;
-wire wb_m2s_cpu0_rom_we;
-wire wb_m2s_cpu0_rom_cyc;
-wire wb_m2s_cpu0_rom_stb;
-wire [2:0] wb_m2s_cpu0_rom_cti;
-wire [1:0] wb_m2s_cpu0_rom_bte;
-wire [31:0] wb_s2m_cpu0_rom_dat;
-wire wb_s2m_cpu0_rom_ack;
-wire wb_s2m_cpu0_rom_err;
-wire wb_s2m_cpu0_rom_rty;
-wire [31:0] wb_m2s_cpu0_ram_adr;
-wire [31:0] wb_m2s_cpu0_ram_dat;
-wire [3:0] wb_m2s_cpu0_ram_sel;
-wire wb_m2s_cpu0_ram_we;
-wire wb_m2s_cpu0_ram_cyc;
-wire wb_m2s_cpu0_ram_stb;
-wire [2:0] wb_m2s_cpu0_ram_cti;
-wire [1:0] wb_m2s_cpu0_ram_bte;
-wire [31:0] wb_s2m_cpu0_ram_dat;
-wire wb_s2m_cpu0_ram_ack;
-wire wb_s2m_cpu0_ram_err;
-wire wb_s2m_cpu0_ram_rty;
-
-wb_interconnect wb_intercon0(
- .wb_clk_i (wb_clk),
- .wb_rst_i (wb_rst),
- .wb_cpu0_ibus_adr_i (wb_m2s_cpu0_ibus_adr),
- .wb_cpu0_ibus_dat_i (wb_m2s_cpu0_ibus_dat),
- .wb_cpu0_ibus_sel_i (wb_m2s_cpu0_ibus_sel),
- .wb_cpu0_ibus_we_i (wb_m2s_cpu0_ibus_we),
- .wb_cpu0_ibus_cyc_i (wb_m2s_cpu0_ibus_cyc),
- .wb_cpu0_ibus_stb_i (wb_m2s_cpu0_ibus_stb),
- .wb_cpu0_ibus_cti_i (wb_m2s_cpu0_ibus_cti),
- .wb_cpu0_ibus_bte_i (wb_m2s_cpu0_ibus_bte),
- .wb_cpu0_ibus_dat_o (wb_s2m_cpu0_ibus_dat),
- .wb_cpu0_ibus_ack_o (wb_s2m_cpu0_ibus_ack),
- .wb_cpu0_ibus_err_o (wb_s2m_cpu0_ibus_err),
- .wb_cpu0_ibus_rty_o (wb_s2m_cpu0_ibus_rty),
- .wb_cpu0_dbus_adr_i (wb_m2s_cpu0_dbus_adr),
- .wb_cpu0_dbus_dat_i (wb_m2s_cpu0_dbus_dat),
- .wb_cpu0_dbus_sel_i (wb_m2s_cpu0_dbus_sel),
- .wb_cpu0_dbus_we_i (wb_m2s_cpu0_dbus_we),
- .wb_cpu0_dbus_cyc_i (wb_m2s_cpu0_dbus_cyc),
- .wb_cpu0_dbus_stb_i (wb_m2s_cpu0_dbus_stb),
- .wb_cpu0_dbus_cti_i (wb_m2s_cpu0_dbus_cti),
- .wb_cpu0_dbus_bte_i (wb_m2s_cpu0_dbus_bte),
- .wb_cpu0_dbus_dat_o (wb_s2m_cpu0_dbus_dat),
- .wb_cpu0_dbus_ack_o (wb_s2m_cpu0_dbus_ack),
- .wb_cpu0_dbus_err_o (wb_s2m_cpu0_dbus_err),
- .wb_cpu0_dbus_rty_o (wb_s2m_cpu0_dbus_rty),
- .wb_mgmt_adr_i (wb_m2s_mgmt_adr),
- .wb_mgmt_dat_i (wb_m2s_mgmt_dat),
- .wb_mgmt_sel_i (wb_m2s_mgmt_sel),
- .wb_mgmt_we_i (wb_m2s_mgmt_we),
- .wb_mgmt_cyc_i (wb_m2s_mgmt_cyc),
- .wb_mgmt_stb_i (wb_m2s_mgmt_stb),
- .wb_mgmt_cti_i (wb_m2s_mgmt_cti),
- .wb_mgmt_bte_i (wb_m2s_mgmt_bte),
- .wb_mgmt_dat_o (wb_s2m_mgmt_dat),
- .wb_mgmt_ack_o (wb_s2m_mgmt_ack),
- .wb_mgmt_err_o (wb_s2m_mgmt_err),
- .wb_mgmt_rty_o (wb_s2m_mgmt_rty),
- .wb_timer0_adr_o (wb_m2s_timer0_adr),
- .wb_timer0_dat_o (wb_m2s_timer0_dat),
- .wb_timer0_sel_o (wb_m2s_timer0_sel),
- .wb_timer0_we_o (wb_m2s_timer0_we),
- .wb_timer0_cyc_o (wb_m2s_timer0_cyc),
- .wb_timer0_stb_o (wb_m2s_timer0_stb),
- .wb_timer0_cti_o (wb_m2s_timer0_cti),
- .wb_timer0_bte_o (wb_m2s_timer0_bte),
- .wb_timer0_dat_i (wb_s2m_timer0_dat),
- .wb_timer0_ack_i (wb_s2m_timer0_ack),
- .wb_timer0_err_i (wb_s2m_timer0_err),
- .wb_timer0_rty_i (wb_s2m_timer0_rty),
- .wb_uart0_adr_o (wb_m2s_uart0_adr),
- .wb_uart0_dat_o (wb_m2s_uart0_dat),
- .wb_uart0_sel_o (wb_m2s_uart0_sel),
- .wb_uart0_we_o (wb_m2s_uart0_we),
- .wb_uart0_cyc_o (wb_m2s_uart0_cyc),
- .wb_uart0_stb_o (wb_m2s_uart0_stb),
- .wb_uart0_cti_o (wb_m2s_uart0_cti),
- .wb_uart0_bte_o (wb_m2s_uart0_bte),
- .wb_uart0_dat_i (wb_s2m_uart0_dat),
- .wb_uart0_ack_i (wb_s2m_uart0_ack),
- .wb_uart0_err_i (wb_s2m_uart0_err),
- .wb_uart0_rty_i (wb_s2m_uart0_rty),
- .wb_led0_adr_o (wb_m2s_led0_adr),
- .wb_led0_dat_o (wb_m2s_led0_dat),
- .wb_led0_sel_o (wb_m2s_led0_sel),
- .wb_led0_we_o (wb_m2s_led0_we),
- .wb_led0_cyc_o (wb_m2s_led0_cyc),
- .wb_led0_stb_o (wb_m2s_led0_stb),
- .wb_led0_cti_o (wb_m2s_led0_cti),
- .wb_led0_bte_o (wb_m2s_led0_bte),
- .wb_led0_dat_i (wb_s2m_led0_dat),
- .wb_led0_ack_i (wb_s2m_led0_ack),
- .wb_led0_err_i (wb_s2m_led0_err),
- .wb_led0_rty_i (wb_s2m_led0_rty),
- .wb_cpu0_rom_adr_o (wb_m2s_cpu0_rom_adr),
- .wb_cpu0_rom_dat_o (wb_m2s_cpu0_rom_dat),
- .wb_cpu0_rom_sel_o (wb_m2s_cpu0_rom_sel),
- .wb_cpu0_rom_we_o (wb_m2s_cpu0_rom_we),
- .wb_cpu0_rom_cyc_o (wb_m2s_cpu0_rom_cyc),
- .wb_cpu0_rom_stb_o (wb_m2s_cpu0_rom_stb),
- .wb_cpu0_rom_cti_o (wb_m2s_cpu0_rom_cti),
- .wb_cpu0_rom_bte_o (wb_m2s_cpu0_rom_bte),
- .wb_cpu0_rom_dat_i (wb_s2m_cpu0_rom_dat),
- .wb_cpu0_rom_ack_i (wb_s2m_cpu0_rom_ack),
- .wb_cpu0_rom_err_i (wb_s2m_cpu0_rom_err),
- .wb_cpu0_rom_rty_i (wb_s2m_cpu0_rom_rty),
- .wb_cpu0_ram_adr_o (wb_m2s_cpu0_ram_adr),
- .wb_cpu0_ram_dat_o (wb_m2s_cpu0_ram_dat),
- .wb_cpu0_ram_sel_o (wb_m2s_cpu0_ram_sel),
- .wb_cpu0_ram_we_o (wb_m2s_cpu0_ram_we),
- .wb_cpu0_ram_cyc_o (wb_m2s_cpu0_ram_cyc),
- .wb_cpu0_ram_stb_o (wb_m2s_cpu0_ram_stb),
- .wb_cpu0_ram_cti_o (wb_m2s_cpu0_ram_cti),
- .wb_cpu0_ram_bte_o (wb_m2s_cpu0_ram_bte),
- .wb_cpu0_ram_dat_i (wb_s2m_cpu0_ram_dat),
- .wb_cpu0_ram_ack_i (wb_s2m_cpu0_ram_ack),
- .wb_cpu0_ram_err_i (wb_s2m_cpu0_ram_err),
- .wb_cpu0_ram_rty_i (wb_s2m_cpu0_ram_rty)
-);
-/***************************************************************************/
+parameter RAM_BASE_ADDRESS = 32'h3000_1000;
+parameter TIMER_BASE_ADDRESS = 32'h3fff_ff00;
+parameter UART_BASE_ADR = 32'h3fff_fe00;
+parameter LED_BASE_ADR = 32'h3fff_fd00;
assign mprj_adr_o = wb_m2s_mgmt_adr;
assign mprj_dat_o = wb_m2s_mgmt_dat;
@@ -397,7 +195,9 @@
// Uart for console logging
`ifndef USE_OBSOLETE_UART
-simpleuart_wb simpleuart (
+simpleuartA_wb #(
+ .BASE_ADR(UART_BASE_ADR)
+) simpleuartA0 (
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wb_adr_i(wb_m2s_uart0_adr),
diff --git a/openlane/user_proj/src/wb_interconnect.v b/openlane/user_proj/src/wb_interconnect.v
index 9bed0be..536e4dc 100644
--- a/openlane/user_proj/src/wb_interconnect.v
+++ b/openlane/user_proj/src/wb_interconnect.v
@@ -1,6 +1,6 @@
-// THIS FILE IS AUTOGENERATED BY wb_intercon_gen
+// THIS FILE IS AUTOGENERATED BY wb_interconA_gen
// ANY MANUAL CHANGES WILL BE LOST
-module wb_interconnect
+module wb_interconA
(input wb_clk_i,
input wb_rst_i,
input [31:0] wb_cpu0_ibus_adr_i,
@@ -267,8 +267,8 @@
wb_mux
#(.num_slaves (5),
- .MATCH_ADDR ({32'h30000000, 32'h30003000, 32'h40000000, 32'h40001000, 32'h40002000}),
- .MATCH_MASK ({32'hfffff800, 32'hfffff800, 32'hfffff000, 32'hfffff000, 32'hfffff000}))
+ .MATCH_ADDR ({32'h30000000, 32'h30001000, 32'h3fffff00, 32'h3ffffe00, 32'h3ffffd00}),
+ .MATCH_MASK ({32'hfffff800, 32'hfffff800, 32'hffffff00, 32'hffffff00, 32'hffffff00}))
wb_mux_cpu0_dbus
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
@@ -299,8 +299,8 @@
wb_mux
#(.num_slaves (5),
- .MATCH_ADDR ({32'h30000000, 32'h30003000, 32'h40000000, 32'h40001000, 32'h40002000}),
- .MATCH_MASK ({32'hfffff800, 32'hfffff800, 32'hfffff000, 32'hfffff000, 32'hfffff000}))
+ .MATCH_ADDR ({32'h30000000, 32'h30001000, 32'h3fffff00, 32'h3ffffe00, 32'h3ffffd00}),
+ .MATCH_MASK ({32'hfffff800, 32'hfffff800, 32'hffffff00, 32'hffffff00, 32'hffffff00}))
wb_mux_mgmt
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
diff --git a/openlane/user_proj/src/wb_interconnect.vh b/openlane/user_proj/src/wb_interconnect.vh
new file mode 100644
index 0000000..f2b4261
--- /dev/null
+++ b/openlane/user_proj/src/wb_interconnect.vh
@@ -0,0 +1,199 @@
+// THIS FILE IS AUTOGENERATED BY wb_interconA_gen
+// ANY MANUAL CHANGES WILL BE LOST
+wire [31:0] wb_m2s_cpu0_ibus_adr;
+wire [31:0] wb_m2s_cpu0_ibus_dat;
+wire [3:0] wb_m2s_cpu0_ibus_sel;
+wire wb_m2s_cpu0_ibus_we;
+wire wb_m2s_cpu0_ibus_cyc;
+wire wb_m2s_cpu0_ibus_stb;
+wire [2:0] wb_m2s_cpu0_ibus_cti;
+wire [1:0] wb_m2s_cpu0_ibus_bte;
+wire [31:0] wb_s2m_cpu0_ibus_dat;
+wire wb_s2m_cpu0_ibus_ack;
+wire wb_s2m_cpu0_ibus_err;
+wire wb_s2m_cpu0_ibus_rty;
+wire [31:0] wb_m2s_cpu0_dbus_adr;
+wire [31:0] wb_m2s_cpu0_dbus_dat;
+wire [3:0] wb_m2s_cpu0_dbus_sel;
+wire wb_m2s_cpu0_dbus_we;
+wire wb_m2s_cpu0_dbus_cyc;
+wire wb_m2s_cpu0_dbus_stb;
+wire [2:0] wb_m2s_cpu0_dbus_cti;
+wire [1:0] wb_m2s_cpu0_dbus_bte;
+wire [31:0] wb_s2m_cpu0_dbus_dat;
+wire wb_s2m_cpu0_dbus_ack;
+wire wb_s2m_cpu0_dbus_err;
+wire wb_s2m_cpu0_dbus_rty;
+wire [31:0] wb_m2s_mgmt_adr;
+wire [31:0] wb_m2s_mgmt_dat;
+wire [3:0] wb_m2s_mgmt_sel;
+wire wb_m2s_mgmt_we;
+wire wb_m2s_mgmt_cyc;
+wire wb_m2s_mgmt_stb;
+wire [2:0] wb_m2s_mgmt_cti;
+wire [1:0] wb_m2s_mgmt_bte;
+wire [31:0] wb_s2m_mgmt_dat;
+wire wb_s2m_mgmt_ack;
+wire wb_s2m_mgmt_err;
+wire wb_s2m_mgmt_rty;
+wire [31:0] wb_m2s_timer0_adr;
+wire [31:0] wb_m2s_timer0_dat;
+wire [3:0] wb_m2s_timer0_sel;
+wire wb_m2s_timer0_we;
+wire wb_m2s_timer0_cyc;
+wire wb_m2s_timer0_stb;
+wire [2:0] wb_m2s_timer0_cti;
+wire [1:0] wb_m2s_timer0_bte;
+wire [31:0] wb_s2m_timer0_dat;
+wire wb_s2m_timer0_ack;
+wire wb_s2m_timer0_err;
+wire wb_s2m_timer0_rty;
+wire [31:0] wb_m2s_uart0_adr;
+wire [31:0] wb_m2s_uart0_dat;
+wire [3:0] wb_m2s_uart0_sel;
+wire wb_m2s_uart0_we;
+wire wb_m2s_uart0_cyc;
+wire wb_m2s_uart0_stb;
+wire [2:0] wb_m2s_uart0_cti;
+wire [1:0] wb_m2s_uart0_bte;
+wire [31:0] wb_s2m_uart0_dat;
+wire wb_s2m_uart0_ack;
+wire wb_s2m_uart0_err;
+wire wb_s2m_uart0_rty;
+wire [31:0] wb_m2s_led0_adr;
+wire [31:0] wb_m2s_led0_dat;
+wire [3:0] wb_m2s_led0_sel;
+wire wb_m2s_led0_we;
+wire wb_m2s_led0_cyc;
+wire wb_m2s_led0_stb;
+wire [2:0] wb_m2s_led0_cti;
+wire [1:0] wb_m2s_led0_bte;
+wire [31:0] wb_s2m_led0_dat;
+wire wb_s2m_led0_ack;
+wire wb_s2m_led0_err;
+wire wb_s2m_led0_rty;
+wire [31:0] wb_m2s_cpu0_rom_adr;
+wire [31:0] wb_m2s_cpu0_rom_dat;
+wire [3:0] wb_m2s_cpu0_rom_sel;
+wire wb_m2s_cpu0_rom_we;
+wire wb_m2s_cpu0_rom_cyc;
+wire wb_m2s_cpu0_rom_stb;
+wire [2:0] wb_m2s_cpu0_rom_cti;
+wire [1:0] wb_m2s_cpu0_rom_bte;
+wire [31:0] wb_s2m_cpu0_rom_dat;
+wire wb_s2m_cpu0_rom_ack;
+wire wb_s2m_cpu0_rom_err;
+wire wb_s2m_cpu0_rom_rty;
+wire [31:0] wb_m2s_cpu0_ram_adr;
+wire [31:0] wb_m2s_cpu0_ram_dat;
+wire [3:0] wb_m2s_cpu0_ram_sel;
+wire wb_m2s_cpu0_ram_we;
+wire wb_m2s_cpu0_ram_cyc;
+wire wb_m2s_cpu0_ram_stb;
+wire [2:0] wb_m2s_cpu0_ram_cti;
+wire [1:0] wb_m2s_cpu0_ram_bte;
+wire [31:0] wb_s2m_cpu0_ram_dat;
+wire wb_s2m_cpu0_ram_ack;
+wire wb_s2m_cpu0_ram_err;
+wire wb_s2m_cpu0_ram_rty;
+
+wb_interconA wb_interconA0
+ (.wb_clk_i (wb_clk),
+ .wb_rst_i (wb_rst),
+ .wb_cpu0_ibus_adr_i (wb_m2s_cpu0_ibus_adr),
+ .wb_cpu0_ibus_dat_i (wb_m2s_cpu0_ibus_dat),
+ .wb_cpu0_ibus_sel_i (wb_m2s_cpu0_ibus_sel),
+ .wb_cpu0_ibus_we_i (wb_m2s_cpu0_ibus_we),
+ .wb_cpu0_ibus_cyc_i (wb_m2s_cpu0_ibus_cyc),
+ .wb_cpu0_ibus_stb_i (wb_m2s_cpu0_ibus_stb),
+ .wb_cpu0_ibus_cti_i (wb_m2s_cpu0_ibus_cti),
+ .wb_cpu0_ibus_bte_i (wb_m2s_cpu0_ibus_bte),
+ .wb_cpu0_ibus_dat_o (wb_s2m_cpu0_ibus_dat),
+ .wb_cpu0_ibus_ack_o (wb_s2m_cpu0_ibus_ack),
+ .wb_cpu0_ibus_err_o (wb_s2m_cpu0_ibus_err),
+ .wb_cpu0_ibus_rty_o (wb_s2m_cpu0_ibus_rty),
+ .wb_cpu0_dbus_adr_i (wb_m2s_cpu0_dbus_adr),
+ .wb_cpu0_dbus_dat_i (wb_m2s_cpu0_dbus_dat),
+ .wb_cpu0_dbus_sel_i (wb_m2s_cpu0_dbus_sel),
+ .wb_cpu0_dbus_we_i (wb_m2s_cpu0_dbus_we),
+ .wb_cpu0_dbus_cyc_i (wb_m2s_cpu0_dbus_cyc),
+ .wb_cpu0_dbus_stb_i (wb_m2s_cpu0_dbus_stb),
+ .wb_cpu0_dbus_cti_i (wb_m2s_cpu0_dbus_cti),
+ .wb_cpu0_dbus_bte_i (wb_m2s_cpu0_dbus_bte),
+ .wb_cpu0_dbus_dat_o (wb_s2m_cpu0_dbus_dat),
+ .wb_cpu0_dbus_ack_o (wb_s2m_cpu0_dbus_ack),
+ .wb_cpu0_dbus_err_o (wb_s2m_cpu0_dbus_err),
+ .wb_cpu0_dbus_rty_o (wb_s2m_cpu0_dbus_rty),
+ .wb_mgmt_adr_i (wb_m2s_mgmt_adr),
+ .wb_mgmt_dat_i (wb_m2s_mgmt_dat),
+ .wb_mgmt_sel_i (wb_m2s_mgmt_sel),
+ .wb_mgmt_we_i (wb_m2s_mgmt_we),
+ .wb_mgmt_cyc_i (wb_m2s_mgmt_cyc),
+ .wb_mgmt_stb_i (wb_m2s_mgmt_stb),
+ .wb_mgmt_cti_i (wb_m2s_mgmt_cti),
+ .wb_mgmt_bte_i (wb_m2s_mgmt_bte),
+ .wb_mgmt_dat_o (wb_s2m_mgmt_dat),
+ .wb_mgmt_ack_o (wb_s2m_mgmt_ack),
+ .wb_mgmt_err_o (wb_s2m_mgmt_err),
+ .wb_mgmt_rty_o (wb_s2m_mgmt_rty),
+ .wb_timer0_adr_o (wb_m2s_timer0_adr),
+ .wb_timer0_dat_o (wb_m2s_timer0_dat),
+ .wb_timer0_sel_o (wb_m2s_timer0_sel),
+ .wb_timer0_we_o (wb_m2s_timer0_we),
+ .wb_timer0_cyc_o (wb_m2s_timer0_cyc),
+ .wb_timer0_stb_o (wb_m2s_timer0_stb),
+ .wb_timer0_cti_o (wb_m2s_timer0_cti),
+ .wb_timer0_bte_o (wb_m2s_timer0_bte),
+ .wb_timer0_dat_i (wb_s2m_timer0_dat),
+ .wb_timer0_ack_i (wb_s2m_timer0_ack),
+ .wb_timer0_err_i (wb_s2m_timer0_err),
+ .wb_timer0_rty_i (wb_s2m_timer0_rty),
+ .wb_uart0_adr_o (wb_m2s_uart0_adr),
+ .wb_uart0_dat_o (wb_m2s_uart0_dat),
+ .wb_uart0_sel_o (wb_m2s_uart0_sel),
+ .wb_uart0_we_o (wb_m2s_uart0_we),
+ .wb_uart0_cyc_o (wb_m2s_uart0_cyc),
+ .wb_uart0_stb_o (wb_m2s_uart0_stb),
+ .wb_uart0_cti_o (wb_m2s_uart0_cti),
+ .wb_uart0_bte_o (wb_m2s_uart0_bte),
+ .wb_uart0_dat_i (wb_s2m_uart0_dat),
+ .wb_uart0_ack_i (wb_s2m_uart0_ack),
+ .wb_uart0_err_i (wb_s2m_uart0_err),
+ .wb_uart0_rty_i (wb_s2m_uart0_rty),
+ .wb_led0_adr_o (wb_m2s_led0_adr),
+ .wb_led0_dat_o (wb_m2s_led0_dat),
+ .wb_led0_sel_o (wb_m2s_led0_sel),
+ .wb_led0_we_o (wb_m2s_led0_we),
+ .wb_led0_cyc_o (wb_m2s_led0_cyc),
+ .wb_led0_stb_o (wb_m2s_led0_stb),
+ .wb_led0_cti_o (wb_m2s_led0_cti),
+ .wb_led0_bte_o (wb_m2s_led0_bte),
+ .wb_led0_dat_i (wb_s2m_led0_dat),
+ .wb_led0_ack_i (wb_s2m_led0_ack),
+ .wb_led0_err_i (wb_s2m_led0_err),
+ .wb_led0_rty_i (wb_s2m_led0_rty),
+ .wb_cpu0_rom_adr_o (wb_m2s_cpu0_rom_adr),
+ .wb_cpu0_rom_dat_o (wb_m2s_cpu0_rom_dat),
+ .wb_cpu0_rom_sel_o (wb_m2s_cpu0_rom_sel),
+ .wb_cpu0_rom_we_o (wb_m2s_cpu0_rom_we),
+ .wb_cpu0_rom_cyc_o (wb_m2s_cpu0_rom_cyc),
+ .wb_cpu0_rom_stb_o (wb_m2s_cpu0_rom_stb),
+ .wb_cpu0_rom_cti_o (wb_m2s_cpu0_rom_cti),
+ .wb_cpu0_rom_bte_o (wb_m2s_cpu0_rom_bte),
+ .wb_cpu0_rom_dat_i (wb_s2m_cpu0_rom_dat),
+ .wb_cpu0_rom_ack_i (wb_s2m_cpu0_rom_ack),
+ .wb_cpu0_rom_err_i (wb_s2m_cpu0_rom_err),
+ .wb_cpu0_rom_rty_i (wb_s2m_cpu0_rom_rty),
+ .wb_cpu0_ram_adr_o (wb_m2s_cpu0_ram_adr),
+ .wb_cpu0_ram_dat_o (wb_m2s_cpu0_ram_dat),
+ .wb_cpu0_ram_sel_o (wb_m2s_cpu0_ram_sel),
+ .wb_cpu0_ram_we_o (wb_m2s_cpu0_ram_we),
+ .wb_cpu0_ram_cyc_o (wb_m2s_cpu0_ram_cyc),
+ .wb_cpu0_ram_stb_o (wb_m2s_cpu0_ram_stb),
+ .wb_cpu0_ram_cti_o (wb_m2s_cpu0_ram_cti),
+ .wb_cpu0_ram_bte_o (wb_m2s_cpu0_ram_bte),
+ .wb_cpu0_ram_dat_i (wb_s2m_cpu0_ram_dat),
+ .wb_cpu0_ram_ack_i (wb_s2m_cpu0_ram_ack),
+ .wb_cpu0_ram_err_i (wb_s2m_cpu0_ram_err),
+ .wb_cpu0_ram_rty_i (wb_s2m_cpu0_ram_rty));
+
diff --git a/openlane/user_proj/src/wb_led.v b/openlane/user_proj/src/wb_led.v
index cc0a93f..5755d18 100644
--- a/openlane/user_proj/src/wb_led.v
+++ b/openlane/user_proj/src/wb_led.v
@@ -24,16 +24,14 @@
// Wishbone register addresses
localparam
wb_r_DATA = 1'b0,
- wb_r_SHIFT = 1'b1,
wb_r_MAX = 1'b1;
// register
reg [31:0] data;
-reg [5:0] shift;
// output generation
always @(posedge i_clk) begin
- o_led <= data[shift];
+ o_led <= data[0];
end
// Since the incoming wishbone address from the CPU increments by 4 bytes, we
@@ -45,7 +43,6 @@
if (i_reset) begin
o_wb_ack <= 0;
data <= 0;
- shift <= 0;
end else begin
// Wishbone interface logic
o_wb_ack <= 1'b0;
@@ -55,14 +52,12 @@
// Register read
case (register_index)
wb_r_DATA: o_wb_dat <= data;
- wb_r_SHIFT:o_wb_dat <= shift;
endcase
// Register write
if (i_wb_we) begin
case (register_index)
wb_r_DATA: data <= i_wb_dat;
- wb_r_SHIFT: shift <= i_wb_dat;
endcase
end
end
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 3405326..ab66b5a 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -20,12 +20,12 @@
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
-#source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
-source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
+#source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
-#source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl
-source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
+source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl
+#source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
set script_dir [file dirname [file normalize [info script]]]
@@ -89,7 +89,8 @@
met2 1100 2100 1783.1 2516.54, \
met3 1100 2100 1783.1 2516.54, \
met4 1100 2100 1783.1 2516.54"
-#set ::env(KLAYOUT_XOR_GDS) 0
+
+set ::env(KLAYOUT_XOR_GDS) 0
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index d87238f..668dd5b 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,8 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
+#PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
+PATTERNS = wb_leds
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
index 5237a05..d186b06 100644
--- a/verilog/dv/io_ports/Makefile
+++ b/verilog/dv/io_ports/Makefile
@@ -50,7 +50,7 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I ../../../openlane/user_proj/src \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
index f7628bc..020ab66 100644
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ b/verilog/dv/io_ports/io_ports_tb.v
@@ -28,8 +28,8 @@
reg power1, power2;
reg power3, power4;
- wire gpio;
- wire [37:0] mprj_io;
+ wire gpio;
+ wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
assign mprj_io_0 = mprj_io[7:0];
@@ -68,19 +68,19 @@
end
initial begin
- // Observe Output pins [7:0]
- wait(mprj_io_0 == 8'h01);
- wait(mprj_io_0 == 8'h02);
- wait(mprj_io_0 == 8'h03);
- wait(mprj_io_0 == 8'h04);
- wait(mprj_io_0 == 8'h05);
- wait(mprj_io_0 == 8'h06);
- wait(mprj_io_0 == 8'h07);
- wait(mprj_io_0 == 8'h08);
- wait(mprj_io_0 == 8'h09);
- wait(mprj_io_0 == 8'h0A);
- wait(mprj_io_0 == 8'hFF);
- wait(mprj_io_0 == 8'h00);
+ // Observe Output pins [7:0]
+ wait(mprj_io_0 == 8'h01);
+ wait(mprj_io_0 == 8'h02);
+ wait(mprj_io_0 == 8'h03);
+ wait(mprj_io_0 == 8'h04);
+ wait(mprj_io_0 == 8'h05);
+ wait(mprj_io_0 == 8'h06);
+ wait(mprj_io_0 == 8'h07);
+ wait(mprj_io_0 == 8'h08);
+ wait(mprj_io_0 == 8'h09);
+ wait(mprj_io_0 == 8'h0A);
+ wait(mprj_io_0 == 8'hFF);
+ wait(mprj_io_0 == 8'h00);
`ifdef GL
$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
@@ -94,12 +94,12 @@
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
- RSTB <= 1'b1; // Release reset
+ RSTB <= 1'b1; // Release reset
#170000;
- CSB = 1'b0; // CSB can be released
+ CSB = 1'b0; // CSB can be released
end
- initial begin // Power-up sequence
+ initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
power3 <= 1'b0;
@@ -146,7 +146,7 @@
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
index ba979f7..bd2d8d0 100644
--- a/verilog/dv/la_test1/Makefile
+++ b/verilog/dv/la_test1/Makefile
@@ -50,7 +50,7 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I ../../../openlane/user_proj/src \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
index 626e390..ae59b9a 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/la_test1/la_test1_tb.v
@@ -24,14 +24,14 @@
module la_test1_tb;
reg clock;
- reg RSTB;
+ reg RSTB;
reg CSB;
reg power1, power2;
- wire gpio;
+ wire gpio;
wire uart_tx;
- wire [37:0] mprj_io;
+ wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
@@ -40,7 +40,7 @@
always #12.5 clock <= (clock === 1'b0);
initial begin
- clock = 0;
+ clock = 0;
end
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
@@ -91,13 +91,13 @@
power2 <= 1'b1;
end
- wire flash_csb;
+ wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD1V8;
- wire VDD3V3;
+ wire VDD3V3;
wire VSS;
assign VDD3V3 = power1;
@@ -121,7 +121,7 @@
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
index 0435500..a8af4c6 100644
--- a/verilog/dv/la_test2/Makefile
+++ b/verilog/dv/la_test2/Makefile
@@ -50,7 +50,7 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I ../../../openlane/user_proj/src \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v
index e09905e..ddbdf72 100644
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ b/verilog/dv/la_test2/la_test2_tb.v
@@ -28,8 +28,8 @@
reg power1, power2;
- wire gpio;
- wire [37:0] mprj_io;
+ wire gpio;
+ wire [37:0] mprj_io;
wire [15:0] checkbits;
assign checkbits = mprj_io[31:16];
@@ -86,13 +86,13 @@
power2 <= 1'b1;
end
- wire flash_csb;
+ wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD1V8;
- wire VDD3V3;
+ wire VDD3V3;
wire VSS;
assign VDD3V3 = power1;
@@ -116,7 +116,7 @@
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index b0e4051..e8af253 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -55,7 +55,7 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(MGMT_SOC_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(MGMT_SOC_RTL_PATH) -I ../../../openlane/user_proj/src \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index 7d2c29a..a8fca32 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -34,7 +34,7 @@
uint32_t testval;
- reg_hkspi_disable = 1; // Shut off the housekeeping SPI,
+// reg_hkspi_disable = 1; // Shut off the housekeeping SPI,
// so we can use the pins.
reg_mprj_datal = 0x00000000;
diff --git a/verilog/dv/wb_leds/.gitignore b/verilog/dv/wb_leds/.gitignore
new file mode 100644
index 0000000..5ca552f
--- /dev/null
+++ b/verilog/dv/wb_leds/.gitignore
@@ -0,0 +1,3 @@
+*hex
+*vcd
+*swp
diff --git a/verilog/dv/wb_leds/Makefile b/verilog/dv/wb_leds/Makefile
new file mode 100644
index 0000000..cc00101
--- /dev/null
+++ b/verilog/dv/wb_leds/Makefile
@@ -0,0 +1,79 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+PDK_ROOT?=/local/home/roman/projects/opencircuitdesign/shuttle4/pdks
+GCC_PATH?=/opt/xpack-riscv-none-embed-gcc/bin
+GCC_PREFIX?=riscv-none-embed
+PDK_PATH?=$(PDK_ROOT)/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = wb_leds
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_RTL_PATH) -I ../../../openlane/user_proj/src \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/wb_leds/wb_leds.c b/verilog/dv/wb_leds/wb_leds.c
new file mode 100644
index 0000000..a54786a
--- /dev/null
+++ b/verilog/dv/wb_leds/wb_leds.c
@@ -0,0 +1,89 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+ Wishbone Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Checks led value through the wishbone port
+*/
+
+#define reg_wb_leds (*(volatile uint32_t*)0x3ffffd00)
+
+void main()
+{
+
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
+
+ // Flag start of the test
+ reg_mprj_datal = 0x00600000;
+
+ // set the led, signalling the end of the test
+ reg_wb_leds = 0xff;
+ if (reg_wb_leds == 0xff) {
+ reg_mprj_datal = 0x00610000;
+ } else {
+ reg_mprj_datal = 0x00600000;
+ }
+}
diff --git a/verilog/dv/wb_leds/wb_leds_tb.v b/verilog/dv/wb_leds/wb_leds_tb.v
new file mode 100644
index 0000000..0086f9f
--- /dev/null
+++ b/verilog/dv/wb_leds/wb_leds_tb.v
@@ -0,0 +1,165 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+
+module wb_leds_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire led;
+ wire [7:0] checkbits;
+
+ assign checkbits = mprj_io[23:16];
+ assign led = mprj_io[25];
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("wb_leds.vcd");
+ $dumpvars(0, wb_leds_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (30) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(checkbits == 8'h 60);
+ $display("Monitor: MPRJ-Logic WB Started");
+ wait(checkbits == 8'h 61);
+
+ // wait for leds to get set
+ wait(led == 1'b0);
+ $display("Monitor: LED=0");
+ wait(led == 1'b1);
+ $display("Monitor: LED=1");
+
+ `ifdef GL
+ $display("Monitor: Test 1 Mega-Project IO (GL) Passed");
+ `else
+ $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #100;
+ power1 <= 1'b1;
+ #100;
+ power2 <= 1'b1;
+ #100;
+ power3 <= 1'b1;
+ #100;
+ power4 <= 1'b1;
+ end
+
+ always @(mprj_io) begin
+ #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (USER_VDD3V3),
+ .vdda2 (USER_VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (USER_VDD1V8),
+ .vccd2 (USER_VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("wb_leds.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
\ No newline at end of file
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 1c784c6..f749903 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -50,7 +50,7 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I ../../../openlane/user_proj/src \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index b32f900..46e13bc 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -67,7 +67,7 @@
end
initial begin
- wait(checkbits == 16'h AB60);
+ wait(checkbits == 16'h AB60);
$display("Monitor: MPRJ-Logic WB Started");
wait(checkbits == 16'h AB61);
`ifdef GL
@@ -134,7 +134,7 @@
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
- .mprj_io (mprj_io),
+ .mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 6e09a5d..17dd6d2 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -33,8 +33,8 @@
`include "../../../openlane/user_proj/src/wb_arbiter.v"
`include "../../../openlane/user_proj/src/wb_mux.v"
`include "../../../openlane/user_proj/src/wb_interconnect.v"
-// `include "../../../openlane/user_proj/src/simpleuart.v"
`include "../../../openlane/user_proj/src/wb_openram_wrapper.v"
`include "../../../openlane/user_proj/src/wb_led.v"
`include "../../../openlane/user_proj/src/timer_wb.v"
+ `include "../../../openlane/user_proj/src/simpleuart.v"
`endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
deleted file mode 100644
index ffde4f1..0000000
--- a/verilog/rtl/user_project_wrapper.v
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-`default_nettype none
-/*
- *-------------------------------------------------------------
- *
- * user_project_wrapper
- *
- * This wrapper enumerates all of the pins available to the
- * user for the user project.
- *
- * An example user project is provided in this wrapper. The
- * example should be removed and replaced with the actual
- * user project.
- *
- *-------------------------------------------------------------
- */
-
-module user_project_wrapper #(
- parameter BITS = 32
-) (
-`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
-`endif
-
- // Wishbone Slave ports (WB MI A)
- input wb_clk_i,
- input wb_rst_i,
- input wbs_stb_i,
- input wbs_cyc_i,
- input wbs_we_i,
- input [3:0] wbs_sel_i,
- input [31:0] wbs_dat_i,
- input [31:0] wbs_adr_i,
- output wbs_ack_o,
- output [31:0] wbs_dat_o,
-
- // Logic Analyzer Signals
- input [127:0] la_data_in,
- output [127:0] la_data_out,
- input [127:0] la_oenb,
-
- // IOs
- input [`MPRJ_IO_PADS-1:0] io_in,
- output [`MPRJ_IO_PADS-1:0] io_out,
- output [`MPRJ_IO_PADS-1:0] io_oeb,
-
- // Analog (direct connection to GPIO pad---use with caution)
- // Note that analog I/O is not available on the 7 lowest-numbered
- // GPIO pads, and so the analog_io indexing is offset from the
- // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
- inout [`MPRJ_IO_PADS-10:0] analog_io,
-
- // Independent clock (on independent integer divider)
- input user_clock2,
-
- // User maskable interrupt signals
- output [2:0] user_irq
-);
-
-/*--------------------------------------*/
-/* User project is instantiated here */
-/*--------------------------------------*/
-
-user_proj mprj (
-`ifdef USE_POWER_PINS
- .vccd1(vccd1), // User area 1 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
-`endif
-
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- // MGMT SoC Wishbone Slave
-
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i),
- .wbs_sel_i(wbs_sel_i),
- .wbs_adr_i(wbs_adr_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_dat_o(wbs_dat_o),
-
- // Logic Analyzer
-
- .la_data_in(la_data_in),
- .la_data_out(la_data_out),
- .la_oenb (la_oenb),
-
- // IO Pads
-
- .io_in (io_in),
- .io_out(io_out),
- .io_oeb(io_oeb),
-
- // IRQ
- .irq(user_irq)
-);
-
-endmodule // user_project_wrapper
-
-`default_nettype wire