tree: 6546bad6b79e10a471aa6d2e68f288ed7760d695 [path history] [tgz]
  1. .github/
  2. docs/
  3. mag/
  4. maglef/
  5. signoff/
  6. .gitignore
  7. .gitmodules
  8. LICENSE
  9. Makefile
  10. README.md
README.md

nMigen+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

  • Minerva RV32IM CPU
  • 512 bytes SRAM
  • (Q)SPI flash for code and data memory using spimemio from picosoc
  • HyperRAM for RAM extension using a derivative of litehyperbus
  • 8-bit GPIO
  • UART, timer, and interrupt controller

Built using: