commit	b96fec9d2c6c26a517da8e8dba0ededfe741b6b7	[log] [tgz]
author	gatecat <gatecat@ds0.me>	Tue Dec 21 21:18:10 2021 +0000
committer	gatecat <gatecat@ds0.me>	Wed Dec 29 15:43:19 2021 +0000
tree	00b36c07e7c49b57132750c83ca519a2d412d1e6
parent	4b231fc78b0df6e04c6f9872b57f4456ab464bfd [diff]

Add GDS and GL Verilog

Signed-off-by: gatecat <gatecat@ds0.me>

gds/user_project_wrapper.gds.gz[Added - diff]
verilog/gl/user_project_core_lambdasoc.v[Added - diff]

2 files changed

tree: 00b36c07e7c49b57132750c83ca519a2d412d1e6

README.md

nMigen+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

Minerva RV32IM CPU
512 bytes SRAM
(Q)SPI flash for code and data memory using spimemio from picosoc
HyperRAM for RAM extension using a derivative of litehyperbus
8-bit GPIO
UART, timer, and interrupt controller

Built using:

nMigen
Yosys+ABC
Coriolis for PnR; with PDKMaster and flexcell used in place of the standard sky130 cells.