tree: 0667b514acb3992e77facbd00424a092438eab1b [path history] [tgz]
  1. .github/
  2. docs/
  3. mag/
  4. maglef/
  5. signoff/
  6. verilog/
  7. .gitignore
  8. .gitmodules
  9. info.yaml
  10. LICENSE
  11. Makefile
  12. README.md
README.md

nMigen+Coriolis Test SoC

This is a submission of a test SoC for MPW4 built from https://github.com/ChipFlow/mpw4

It contains:

  • Minerva RV32IM CPU
  • 512 bytes SRAM
  • (Q)SPI flash for code and data memory using spimemio from picosoc
  • HyperRAM for RAM extension using a derivative of litehyperbus
  • 8-bit GPIO
  • UART, timer, and interrupt controller

Built using: