| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m5s,0h4m14s,48162.962962962956,0.27,24081.481481481478,39,623.69,6502,0,0,0,0,0,0,0,6,0,0,0,365524,56020,-0.56,-0.56,-0.72,-0.72,-0.78,-16.15,-16.15,-136.64,-136.64,-161.07,297911924,0.0,53.29,21.57,24.67,0.05,-1,6477,6647,1150,1320,0,0,0,6502,131,107,82,107,352,213,29,2197,1190,1123,28,204,3274,0,3478,92.7643784786642,10.78,10,AREA 0,5,50,1,50,153.18,0.52,0,sky130_fd_sc_hd,4,4 |
