jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/logs/precheck.log - third_party/shuttle/sky130/mpw-004/slot-028 - Git at Google

 2021-12-23 08:47:04 - [INFO] - {{Project Git Info}} Repository: https://github.com/Univisiontechnocon-com/yifive_a2.git | Branch: master | Commit: 90a79643bee035a55bba951bb8e3af6783cbe2e2
 2021-12-23 08:47:04 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: yifive_a2
 2021-12-23 08:47:10 - [INFO] - {{Project GDS Info}} user_project_wrapper: bc427c38990099ead6a8f7801f9fd1fe19fc1325
 2021-12-23 08:47:10 - [INFO] - {{Tools Info}} KLayout: v0.27.5 | Magic: v8.3.243
 2021-12-23 08:47:10 - [INFO] - {{PDKs Info}} Open PDKs: 13207762cf4eb2e2943be51bf1605f2bb2bac41d | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 2021-12-23 08:47:10 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'yifive_a2/jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/logs'
 2021-12-23 08:47:10 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
 2021-12-23 08:47:10 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
 2021-12-23 08:47:11 - [INFO] - An approved LICENSE (Apache-2.0) was found in yifive_a2.
 2021-12-23 08:47:11 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
 2021-12-23 08:47:12 - [INFO] - An approved LICENSE (Apache-2.0) was found in yifive_a2.
 2021-12-23 08:47:12 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/dv/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v): 'utf-8' codec can't decode byte 0x91 in position 5970: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv): 'utf-8' codec can't decode byte 0xa9 in position 4875: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh): 'utf-8' codec can't decode byte 0xa9 in position 4377: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
 2021-12-23 08:47:14 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 285 non-compliant file(s) with the SPDX Standard.
 2021-12-23 08:47:14 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['yifive_a2/Makefile', 'yifive_a2/sta/Makefile', 'yifive_a2/sta/run_sta', 'yifive_a2/sta/scripts/or_write_verilog.tcl', 'yifive_a2/sta/scripts/sta.tcl', 'yifive_a2/sta/scripts/caravel_timing.tcl.1', 'yifive_a2/sta/scripts/caravel_timing.tcl', 'yifive_a2/sta/sdc/caravel.sdc', 'yifive_a2/verilog/dv/Makefile', 'yifive_a2/verilog/dv/risc_boot/risc_boot.c', 'yifive_a2/verilog/dv/risc_boot/risc_boot_tb.v', 'yifive_a2/verilog/dv/risc_boot/Makefile', 'yifive_a2/verilog/dv/risc_boot/user_uart.c', 'yifive_a2/verilog/dv/risc_boot/run_iverilog', 'yifive_a2/verilog/dv/vpi/system/system.c']
 2021-12-23 08:47:14 - [INFO] - For the full SPDX compliance report check: yifive_a2/jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/logs/spdx_compliance_report.log
 2021-12-23 08:47:14 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
 2021-12-23 08:47:14 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
 2021-12-23 08:47:14 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
 2021-12-23 08:47:14 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
 2021-12-23 08:47:17 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
 2021-12-23 08:47:17 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
 2021-12-23 08:47:17 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
 2021-12-23 08:47:17 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
 2021-12-23 08:47:17 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/verilog/rtl/__user_project_wrapper.v
 2021-12-23 08:47:17 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/verilog/rtl/__user_project_wrapper.v
 2021-12-23 08:47:17 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/verilog/rtl/defines.v
 2021-12-23 08:47:18 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/verilog/rtl/defines.v
 2021-12-23 08:47:25 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel.
 2021-12-23 08:47:25 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances).
 2021-12-23 08:47:25 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
 2021-12-23 08:47:25 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
 2021-12-23 08:47:25 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
 2021-12-23 08:47:25 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
 2021-12-23 08:47:25 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
 2021-12-23 08:47:25 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (14 instances).
 2021-12-23 08:47:25 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
 2021-12-23 08:47:25 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
 2021-12-23 08:47:25 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
 2021-12-23 08:47:25 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
 2021-12-23 08:47:25 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
 2021-12-23 08:47:25 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
 2021-12-23 08:47:25 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
 2021-12-23 08:47:25 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/gds/user_project_wrapper_empty.gds.gz
 2021-12-23 08:47:25 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/gds/user_project_wrapper_empty.gds.gz
 2021-12-23 08:49:54 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view yifive_a2/jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/outputs/user_project_wrapper.xor.gds
 2021-12-23 08:49:54 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
 2021-12-23 08:49:54 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
 2021-12-23 09:07:28 - [INFO] - 0 DRC violations
 2021-12-23 09:07:28 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2021-12-23 09:07:28 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
 2021-12-23 09:08:57 - [INFO] - No DRC Violations found
 2021-12-23 09:08:57 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2021-12-23 09:08:57 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
 2021-12-23 09:26:15 - [INFO] - No DRC Violations found
 2021-12-23 09:26:15 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2021-12-23 09:26:15 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
 2021-12-23 09:29:06 - [INFO] - No DRC Violations found
 2021-12-23 09:29:06 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2021-12-23 09:29:06 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
 2021-12-23 09:30:21 - [INFO] - No DRC Violations found
 2021-12-23 09:30:21 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2021-12-23 09:30:21 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
 2021-12-23 09:30:54 - [INFO] - No DRC Violations found
 2021-12-23 09:30:54 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2021-12-23 09:30:54 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
 2021-12-23 09:31:06 - [INFO] - No DRC Violations found
 2021-12-23 09:31:06 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2021-12-23 09:31:06 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'yifive_a2/jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/logs'
 2021-12-23 09:31:06 - [INFO] - {{SUCCESS}} All Checks Passed !!!
	2021-12-23 08:47:04 - [INFO] - {{Project Git Info}} Repository: https://github.com/Univisiontechnocon-com/yifive_a2.git \| Branch: master \| Commit: 90a79643bee035a55bba951bb8e3af6783cbe2e2
	2021-12-23 08:47:04 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: yifive_a2
	2021-12-23 08:47:10 - [INFO] - {{Project GDS Info}} user_project_wrapper: bc427c38990099ead6a8f7801f9fd1fe19fc1325
	2021-12-23 08:47:10 - [INFO] - {{Tools Info}} KLayout: v0.27.5 \| Magic: v8.3.243
	2021-12-23 08:47:10 - [INFO] - {{PDKs Info}} Open PDKs: 13207762cf4eb2e2943be51bf1605f2bb2bac41d \| Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
	2021-12-23 08:47:10 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'yifive_a2/jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/logs'
	2021-12-23 08:47:10 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
	2021-12-23 08:47:10 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
	2021-12-23 08:47:11 - [INFO] - An approved LICENSE (Apache-2.0) was found in yifive_a2.
	2021-12-23 08:47:11 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
	2021-12-23 08:47:12 - [INFO] - An approved LICENSE (Apache-2.0) was found in yifive_a2.
	2021-12-23 08:47:12 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/dv/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v): 'utf-8' codec can't decode byte 0x91 in position 5970: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv): 'utf-8' codec can't decode byte 0xa9 in position 4875: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh): 'utf-8' codec can't decode byte 0xa9 in position 4377: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:12 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (yifive_a2/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv): 'utf-8' codec can't decode byte 0xa9 in position 120: invalid start byte
	2021-12-23 08:47:14 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 285 non-compliant file(s) with the SPDX Standard.
	2021-12-23 08:47:14 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['yifive_a2/Makefile', 'yifive_a2/sta/Makefile', 'yifive_a2/sta/run_sta', 'yifive_a2/sta/scripts/or_write_verilog.tcl', 'yifive_a2/sta/scripts/sta.tcl', 'yifive_a2/sta/scripts/caravel_timing.tcl.1', 'yifive_a2/sta/scripts/caravel_timing.tcl', 'yifive_a2/sta/sdc/caravel.sdc', 'yifive_a2/verilog/dv/Makefile', 'yifive_a2/verilog/dv/risc_boot/risc_boot.c', 'yifive_a2/verilog/dv/risc_boot/risc_boot_tb.v', 'yifive_a2/verilog/dv/risc_boot/Makefile', 'yifive_a2/verilog/dv/risc_boot/user_uart.c', 'yifive_a2/verilog/dv/risc_boot/run_iverilog', 'yifive_a2/verilog/dv/vpi/system/system.c']
	2021-12-23 08:47:14 - [INFO] - For the full SPDX compliance report check: yifive_a2/jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/logs/spdx_compliance_report.log
	2021-12-23 08:47:14 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
	2021-12-23 08:47:14 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
	2021-12-23 08:47:14 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
	2021-12-23 08:47:14 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
	2021-12-23 08:47:17 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
	2021-12-23 08:47:17 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
	2021-12-23 08:47:17 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
	2021-12-23 08:47:17 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
	2021-12-23 08:47:17 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/verilog/rtl/__user_project_wrapper.v
	2021-12-23 08:47:17 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/verilog/rtl/__user_project_wrapper.v
	2021-12-23 08:47:17 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/verilog/rtl/defines.v
	2021-12-23 08:47:18 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/verilog/rtl/defines.v
	2021-12-23 08:47:25 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel.
	2021-12-23 08:47:25 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances).
	2021-12-23 08:47:25 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
	2021-12-23 08:47:25 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
	2021-12-23 08:47:25 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
	2021-12-23 08:47:25 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
	2021-12-23 08:47:25 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
	2021-12-23 08:47:25 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (14 instances).
	2021-12-23 08:47:25 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
	2021-12-23 08:47:25 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
	2021-12-23 08:47:25 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
	2021-12-23 08:47:25 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
	2021-12-23 08:47:25 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
	2021-12-23 08:47:25 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
	2021-12-23 08:47:25 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
	2021-12-23 08:47:25 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/gds/user_project_wrapper_empty.gds.gz
	2021-12-23 08:47:25 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/6b61d51f8b3a742155b2c66fb1be4e76794ce9ea/gds/user_project_wrapper_empty.gds.gz
	2021-12-23 08:49:54 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view yifive_a2/jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/outputs/user_project_wrapper.xor.gds
	2021-12-23 08:49:54 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
	2021-12-23 08:49:54 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
	2021-12-23 09:07:28 - [INFO] - 0 DRC violations
	2021-12-23 09:07:28 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2021-12-23 09:07:28 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
	2021-12-23 09:08:57 - [INFO] - No DRC Violations found
	2021-12-23 09:08:57 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2021-12-23 09:08:57 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
	2021-12-23 09:26:15 - [INFO] - No DRC Violations found
	2021-12-23 09:26:15 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2021-12-23 09:26:15 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
	2021-12-23 09:29:06 - [INFO] - No DRC Violations found
	2021-12-23 09:29:06 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2021-12-23 09:29:06 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
	2021-12-23 09:30:21 - [INFO] - No DRC Violations found
	2021-12-23 09:30:21 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2021-12-23 09:30:21 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
	2021-12-23 09:30:54 - [INFO] - No DRC Violations found
	2021-12-23 09:30:54 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2021-12-23 09:30:54 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
	2021-12-23 09:31:06 - [INFO] - No DRC Violations found
	2021-12-23 09:31:06 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2021-12-23 09:31:06 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'yifive_a2/jobs/mpw_precheck/b7342c38-f73e-4376-be0b-a0979ad0eada/logs'
	2021-12-23 09:31:06 - [INFO] - {{SUCCESS}} All Checks Passed !!!