| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h51m11s,0h28m28s,34498.88888888888,1.8,17249.44444444444,23,1210.03,31049,0,0,0,0,0,0,0,76,9,-1,0,1617218,250691,-4.42,-4.42,-4.38,-4.38,-4.45,-34.56,-34.56,-34.86,-34.86,-35.41,1349556396,0.0,18.48,16.7,4.85,0.56,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,0,23702,69.20415224913495,14.45,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3 |
