| ############################################################################### |
| # Created by write_sdc |
| # Wed Nov 3 17:18:11 2021 |
| ############################################################################### |
| current_design scr1_top_wb |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name core_clk -period 20.0000 [get_ports {core_clk}] |
| set_propagated_clock [get_clocks {core_clk}] |
| create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}] |
| set_propagated_clock [get_clocks {rtc_clk}] |
| create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] |
| set_propagated_clock [get_clocks {wb_clk}] |
| |
| #Reset |
| set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {cpu_rst_n}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {cpu_rst_n}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {pwrup_rst_n}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {rst_n}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {soft_irq}] |
| set_input_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}] |
| |
| set_input_delay -min 1.000 -clock [get_clocks {core_clk}] -add_delay [get_ports {cpu_rst_n}] |
| set_input_delay -min 1.000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {cpu_rst_n}] |
| set_input_delay -min 1.000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {pwrup_rst_n}] |
| set_input_delay -min 1.000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {rst_n}] |
| set_input_delay -min 1.000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {soft_irq}] |
| set_input_delay -min 1.000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}] |
| |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[0]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[10]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[11]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[12]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[13]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[14]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[15]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[16]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[17]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[18]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[19]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[1]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[20]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[21]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[22]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[23]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[24]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[25]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[26]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[27]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[28]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[29]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[2]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[30]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[31]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[3]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[4]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[5]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[6]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[7]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[8]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[9]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_ack_i}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[0]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[10]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[11]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[12]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[13]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[14]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[15]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[16]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[17]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[18]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[19]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[1]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[20]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[21]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[22]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[23]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[24]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[25]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[26]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[27]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[28]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[29]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[2]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[30]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[31]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[3]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[4]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[5]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[6]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[7]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[8]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[9]}] |
| set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_err_i}] |
| |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[0]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[10]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[11]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[12]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[13]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[14]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[15]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[16]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[17]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[18]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[19]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[1]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[20]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[21]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[22]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[23]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[24]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[25]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[26]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[27]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[28]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[29]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[2]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[30]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[31]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[3]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[4]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[5]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[6]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[7]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[8]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[9]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_ack_i}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[0]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[10]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[11]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[12]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[13]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[14]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[15]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[16]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[17]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[18]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[19]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[1]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[20]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[21]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[22]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[23]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[24]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[25]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[26]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[27]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[28]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[29]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[2]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[30]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[31]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[3]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[4]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[5]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[6]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[7]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[8]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[9]}] |
| set_input_delay -min 1.0 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_err_i}] |
| |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[0]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[10]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[11]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[12]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[13]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[14]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[15]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[16]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[17]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[18]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[19]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[1]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[20]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[21]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[22]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[23]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[24]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[25]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[26]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[27]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[28]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[29]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[2]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[30]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[31]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[3]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[4]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[5]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[6]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[7]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[8]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[9]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[0]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[10]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[11]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[12]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[13]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[14]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[15]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[16]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[17]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[18]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[19]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[1]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[20]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[21]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[22]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[23]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[24]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[25]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[26]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[27]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[28]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[29]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[2]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[30]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[31]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[3]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[4]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[5]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[6]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[7]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[8]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[9]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[0]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[1]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[2]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[3]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[0]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[10]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[11]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[12]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[13]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[14]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[15]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[16]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[17]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[18]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[19]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[1]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[20]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[21]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[22]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[23]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[24]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[25]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[26]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[27]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[28]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[29]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[2]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[30]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[31]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[3]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[4]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[5]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[6]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[7]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[8]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[9]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[0]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[10]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[11]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[12]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[13]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[14]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[15]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[16]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[17]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[18]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[19]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[1]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[20]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[21]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[22]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[23]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[24]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[25]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[26]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[27]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[28]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[29]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[2]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[30]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[31]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[3]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[4]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[5]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[6]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[7]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[8]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[9]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[0]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[1]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[2]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[3]}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_stb_o}] |
| set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_we_o}] |
| |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_stb_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_we_o}] |
| |
| ## Max Delay constraints |
| set_max_delay -from [get_ports {wbd_clk_int}] 10 |
| set_max_delay -to [get_ports {wbd_clk_riscv}] 10 |
| set_max_delay -from [get_ports {cfg_cska_riscv[0]}] 10 |
| set_max_delay -from [get_ports {cfg_cska_riscv[1]}] 10 |
| set_max_delay -from [get_ports {cfg_cska_riscv[2]}] 10 |
| set_max_delay -from [get_ports {cfg_cska_riscv[3]}] 10 |
| |
| set_max_delay -from [get_ports {fuse_mhartid[0]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[10]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[11]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[12]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[13]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[14]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[15]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[16]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[17]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[18]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[19]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[1]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[20]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[21]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[22]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[23]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[24]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[25]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[26]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[27]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[28]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[29]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[2]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[30]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[31]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[3]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[4]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[5]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[6]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[7]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[8]}] 10 |
| set_max_delay -from [get_ports {fuse_mhartid[9]}] 10 |
| set_max_delay -from [get_ports {irq_lines[0]}] 10 |
| set_max_delay -from [get_ports {irq_lines[10]}] 10 |
| set_max_delay -from [get_ports {irq_lines[11]}] 10 |
| set_max_delay -from [get_ports {irq_lines[12]}] 10 |
| set_max_delay -from [get_ports {irq_lines[13]}] 10 |
| set_max_delay -from [get_ports {irq_lines[14]}] 10 |
| set_max_delay -from [get_ports {irq_lines[15]}] 10 |
| set_max_delay -from [get_ports {irq_lines[1]}] 10 |
| set_max_delay -from [get_ports {irq_lines[2]}] 10 |
| set_max_delay -from [get_ports {irq_lines[3]}] 10 |
| set_max_delay -from [get_ports {irq_lines[4]}] 10 |
| set_max_delay -from [get_ports {irq_lines[5]}] 10 |
| set_max_delay -from [get_ports {irq_lines[6]}] 10 |
| set_max_delay -from [get_ports {irq_lines[7]}] 10 |
| set_max_delay -from [get_ports {irq_lines[8]}] 10 |
| set_max_delay -from [get_ports {irq_lines[9]}] 10 |
| |
| set_max_delay -to [get_ports {riscv_debug[0]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[10]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[11]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[12]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[13]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[14]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[15]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[16]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[17]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[18]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[19]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[1]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[20]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[21]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[22]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[23]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[24]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[25]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[26]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[27]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[28]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[29]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[2]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[30]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[31]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[32]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[33]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[34]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[35]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[36]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[37]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[38]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[39]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[3]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[40]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[41]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[42]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[43]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[44]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[45]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[46]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[47]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[48]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[49]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[4]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[50]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[51]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[52]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[53]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[54]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[55]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[56]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[57]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[58]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[59]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[5]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[60]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[61]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[62]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[63]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[6]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[7]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[8]}] 10 |
| set_max_delay -to [get_ports {riscv_debug[9]}] 10 |
| |
| set_max_delay -from [get_ports {soft_irq}] 20 |
| |
| set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}] -setup 0.2000 |
| |
| set_clock_groups -name async_clock -asynchronous \ |
| -group [get_clocks {core_clk}]\ |
| -group [get_clocks {rtc_clk}]\ |
| -group [get_clocks {wb_clk}] -comment {Async Clock group} |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {wbd_clk_riscv}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_stb_o}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_we_o}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_stb_o}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_we_o}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[63]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[62]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[61]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[60]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[59]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[58]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[57]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[56]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[55]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[54]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[53]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[52]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[51]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[50]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[49]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[48]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[47]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[46]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[45]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[44]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[43]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[42]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[41]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[40]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[39]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[38]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[37]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[36]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[35]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[34]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[33]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[32]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[31]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[30]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[29]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[28]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[27]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[26]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[25]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[24]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[23]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[22]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[21]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[20]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[19]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[18]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[17]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[16]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[15]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[14]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[13]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[12]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[11]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[10]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[9]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[8]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[7]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[6]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[5]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[4]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[3]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[2]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[1]}] |
| set_load -pin_load 0.0334 [get_ports {riscv_debug[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {soft_irq}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_err_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_err_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_riscv[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_riscv[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_riscv[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_riscv[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[0]}] |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
