openlane/glbl_cfg/base.sdc

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# Created by write_sdc
# Sat Nov 13 06:33:41 2021
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current_design glbl_cfg
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# Timing Constraints
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create_clock -name mclk -period 10.0000 [get_ports {mclk}]

set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.2500 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]


set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[0]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[1]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[2]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[3]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[4]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[5]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[6]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[7]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[0]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[1]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[2]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[3]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[0]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[10]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[11]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[12]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[13]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[14]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[15]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[16]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[17]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[18]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[19]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[1]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[20]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[21]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[22]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[23]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[24]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[25]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[26]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[27]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[28]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[29]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[2]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[30]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[31]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[3]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[4]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[5]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[6]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[7]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[8]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[9]}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reset_n}]
set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {sdr_init_done}]

set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[0]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[1]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[2]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[3]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[4]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[5]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[6]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[7]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[0]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[1]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[2]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[3]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[0]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[10]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[11]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[12]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[13]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[14]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[15]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[16]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[17]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[18]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[19]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[1]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[20]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[21]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[22]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[23]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[24]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[25]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[26]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[27]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[28]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[29]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[2]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[30]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[31]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[3]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[4]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[5]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[6]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[7]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[8]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[9]}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reset_n}]
set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {sdr_init_done}]

set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_en}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[10]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[11]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[12]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[4]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[5]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[6]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[7]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[8]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[9]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[10]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[11]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[4]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[5]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[6]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[7]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[8]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[9]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[10]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[11]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[12]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[13]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[14]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[15]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[16]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[17]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[18]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[19]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[20]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[21]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[22]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[23]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[24]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[25]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[26]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[27]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[28]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[29]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[30]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[31]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[4]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[5]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[6]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[7]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[8]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[9]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[10]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[11]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[12]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[13]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[14]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[15]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[4]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[5]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[6]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[7]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[8]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[9]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[10]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[11]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[12]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[13]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[14]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[15]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[16]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[17]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[18]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[19]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[20]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[21]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[22]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[23]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[24]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[25]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[26]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[27]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[28]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[29]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[30]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[31]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[4]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[5]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[6]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[7]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[8]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[9]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {soft_irq}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[2]}]

set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_en}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[10]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[11]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[12]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[4]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[5]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[6]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[7]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[8]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[9]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[10]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[11]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[4]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[5]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[6]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[7]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[8]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[9]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[10]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[11]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[12]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[13]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[14]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[15]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[16]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[17]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[18]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[19]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[20]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[21]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[22]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[23]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[24]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[25]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[26]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[27]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[28]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[29]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[30]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[31]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[4]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[5]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[6]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[7]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[8]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[9]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[10]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[11]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[12]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[13]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[14]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[15]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[4]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[5]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[6]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[7]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[8]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[9]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[10]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[11]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[12]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[13]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[14]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[15]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[16]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[17]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[18]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[19]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[20]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[21]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[22]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[23]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[24]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[25]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[26]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[27]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[28]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[29]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[2]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[30]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[31]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[3]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[4]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[5]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[6]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[7]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[8]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[9]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {soft_irq}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[0]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[1]}]
set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[2]}]
###############################################################################
# Environment
###############################################################################
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
set_load  $cap_load [all_outputs]

set ::env(SYNTH_TIMING_DERATE) 0.05
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
###############################################################################
# Design Rules
###############################################################################