| ############################################################################### |
| # Created by write_sdc |
| # Sat Nov 13 06:45:14 2021 |
| ############################################################################### |
| current_design wb_interconnect |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name clk_i -period 10.0000 [get_ports {clk_i}] |
| set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2000 |
| |
| set_false_path -from [get_ports {cfg_cska_wi[0]}] |
| set_false_path -from [get_ports {cfg_cska_wi[1]}] |
| set_false_path -from [get_ports {cfg_cska_wi[2]}] |
| set_false_path -from [get_ports {cfg_cska_wi[3]}] |
| |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[3]}] |
| set_input_delay -max 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {rst_n}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[0]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[10]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[11]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[12]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[13]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[14]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[15]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[16]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[17]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[18]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[19]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[1]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[20]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[21]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[22]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[23]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[24]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[25]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[26]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[27]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[28]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[29]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[2]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[30]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[31]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[3]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[4]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[5]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[6]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[7]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[8]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[9]}] |
| set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbd_clk_int}] |
| |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {rst_n}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[0]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[10]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[11]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[12]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[13]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[14]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[15]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[16]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[17]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[18]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[19]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[1]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[20]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[21]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[22]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[23]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[24]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[25]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[26]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[27]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[28]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[29]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[2]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[30]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[31]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[3]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[4]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[5]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[6]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[7]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[8]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[9]}] |
| set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbd_clk_int}] |
| |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_ack_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_err_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_ack_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_err_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_stb_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_we_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_stb_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_we_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_stb_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_we_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[10]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[11]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[12]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[13]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[14]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[15]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[16]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[17]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[18]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[19]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[20]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[21]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[22]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[23]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[24]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[25]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[26]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[27]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[28]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[29]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[30]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[31]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[4]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[5]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[6]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[7]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[8]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[9]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[0]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[1]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[2]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[3]}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_stb_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_we_o}] |
| set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbd_clk_wi}] |
| |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_ack_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_err_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_ack_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_err_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_stb_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_we_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_stb_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_we_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_stb_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_we_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[10]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[11]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[12]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[13]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[14]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[15]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[16]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[17]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[18]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[19]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[20]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[21]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[22]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[23]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[24]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[25]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[26]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[27]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[28]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[29]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[30]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[31]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[4]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[5]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[6]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[7]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[8]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[9]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[0]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[1]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[2]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[3]}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_stb_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_we_o}] |
| set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {wbd_clk_wi}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_ack_o}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_err_o}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_ack_o}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_err_o}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_cyc_o}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_stb_o}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_we_o}] |
| set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[31]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[30]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[29]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[28]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[27]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[26]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[25]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[24]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[23]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[22]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[21]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[20]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[19]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[18]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[17]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[16]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[15]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[14]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[13]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[12]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[11]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[10]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[9]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[8]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[7]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[6]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[5]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[4]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[0]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[3]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[2]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[1]}] |
| set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_cyc_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_stb_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_we_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_cyc_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_stb_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_we_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_cyc_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_stb_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_we_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[0]}] |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
