removed caravel link
diff --git a/.gitmodules b/.gitmodules index 4668a64..3e46499 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -8,6 +8,3 @@ [submodule "verilog/rtl/syntacore/scr1/dependencies/coremark"] path = verilog/rtl/syntacore/scr1/dependencies/coremark url = https://github.com/eembc/coremark -[submodule "caravel"] - path = caravel - url = https://github.com/efabless/caravel-lite.git
diff --git a/caravel b/caravel deleted file mode 160000 index 0f16ba8..0000000 --- a/caravel +++ /dev/null
@@ -1 +0,0 @@ -Subproject commit 0f16ba8eaae841a6f122fc0d5837005d3312fd2b
diff --git a/openlane/uart/base.sdc b/openlane/uart/base.sdc deleted file mode 100644 index b64ad61..0000000 --- a/openlane/uart/base.sdc +++ /dev/null
@@ -1,72 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - - -set_units -time ns -set ::env(CORE_CLOCK_PERIOD) "10" -set ::env(CORE_CLOCK_PORT) "app_clk" -set ::env(CORE_CLOCK_NAME) "app_clk" - -set ::env(LINE_CLOCK_PERIOD) "100" -set ::env(LINE_CLOCK_PORT) "u_lineclk_buf/X" -set ::env(LINE_CLOCK_NAME) "line_clk" - -###################################### -# WB Clock domain input output -###################################### -create_clock [get_ports $::env(CORE_CLOCK_PORT)] -name $::env(CORE_CLOCK_NAME) -period $::env(CORE_CLOCK_PERIOD) -create_clock [get_pins $::env(LINE_CLOCK_PORT)] -name $::env(LINE_CLOCK_NAME) -period $::env(LINE_CLOCK_PERIOD) - -set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6] -set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6] - -set line_input_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6] -set line_output_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6] -puts "\[INFO\]: Setting wb output delay to:$core_output_delay_value" -puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value" - - -set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {arst_n} - -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*] -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*] -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wr*] -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_be*] -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wdata*] - - -set_output_delay $core_output_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_rdata*] -set_output_delay $core_output_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_ack*] - -set_input_delay $line_input_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_in*] -set_output_delay $line_input_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_oeb*] -set_output_delay $line_output_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_out*] - - -set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(LINE_CLOCK_NAME)] - -set_clock_uncertainty -from $::env(CORE_CLOCK_NAME) -to $::env(CORE_CLOCK_NAME) -setup 0.400 -set_clock_uncertainty -from $::env(LINE_CLOCK_NAME) -to $::env(LINE_CLOCK_NAME) -setup 0.400 - -set_clock_uncertainty -from $::env(CORE_CLOCK_NAME) -to $::env(CORE_CLOCK_NAME) -hold 0.050 -set_clock_uncertainty -from $::env(LINE_CLOCK_NAME) -to $::env(LINE_CLOCK_NAME) -hold 0.050 - -# TODO set this as parameter -set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] -set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] -puts "\[INFO\]: Setting load to: $cap_load" -set_load $cap_load [all_outputs] -
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl deleted file mode 100644 index b1eadeb..0000000 --- a/openlane/uart/config.tcl +++ /dev/null
@@ -1,91 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - -# Global -# ------ - -set script_dir [file dirname [file normalize [info script]]] -# Name -set ::env(DESIGN_NAME) uart_core - - -set ::env(DESIGN_IS_CORE) "0" -set ::env(FP_PDN_CORE_RING) "0" - -# Timing configuration -set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "app_clk" - -set ::env(SYNTH_MAX_FANOUT) 4 - -# Sources -# ------- - -# Local sources + no2usb sources -set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/uart/src/uart_core.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \ - $script_dir/../../verilog/rtl/lib/async_fifo_th.sv \ - $script_dir/../../verilog/rtl/lib/reset_sync.sv \ - $script_dir/../../verilog/rtl/lib/double_sync_low.v \ - $script_dir/../../verilog/rtl/lib/clk_ctl.v \ - $script_dir/../../verilog/rtl/lib/registers.v \ - " - -set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -#set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ] - -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" - -set ::env(LEC_ENABLE) 0 - -set ::env(VDD_PIN) [list {vccd1}] -set ::env(GND_PIN) [list {vssd1}] - - -# Floorplanning -# ------------- - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg -set ::env(FP_SIZING) "absolute" -set ::env(DIE_AREA) [list 0.0 0.0 300.0 400.0] - - - -# If you're going to use multiple power domains, then keep this disabled. -set ::env(RUN_CVC) 0 - -#set ::env(PDN_CFG) $script_dir/pdn.tcl - - -set ::env(PL_ROUTABILITY_DRIVEN) 1 - -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 - - -set ::env(GLB_RT_MAXLAYER) 4 -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 - -set ::env(DIODE_INSERTION_STRATEGY) 4 - -set ::env(FP_PDN_VPITCH) 100 -set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/uart/pdn.tcl b/openlane/uart/pdn.tcl deleted file mode 100644 index 1fe689b..0000000 --- a/openlane/uart/pdn.tcl +++ /dev/null
@@ -1,49 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -# Power nets -set ::power_nets $::env(VDD_PIN) -set ::ground_nets $::env(GND_PIN) - -set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5" - -pdngen::specify_grid stdcell { - name grid - rails { - met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} - } - straps { - met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} - met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} - } - connect {{met1 met4} {met4 met5}} -} - -pdngen::specify_grid macro { - power_pins "VPWR" - ground_pins "VGND" - blockages "li1 met1 met2 met3 met4" - straps { - } - connect {{met4_PIN_ver met5}} -} - -set ::halo 5 - -# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area -set ::rails_start_with "POWER" ; - -# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area -set ::stripes_start_with "POWER" ;
diff --git a/openlane/uart/pin_order.cfg b/openlane/uart/pin_order.cfg deleted file mode 100644 index 248595c..0000000 --- a/openlane/uart/pin_order.cfg +++ /dev/null
@@ -1,38 +0,0 @@ -#BUS_SORT -#MANUAL_PLACE - -#S -app_clk 0000 0 -arst_n -io_in\[1\] -io_out\[1\] -io_oeb\[1\] -io_in\[0\] -io_out\[0\] -io_oeb\[0\] - -#N -reg_cs 0000 0 -reg_wr 0000 1 -reg_addr\[3\] 0000 4 -reg_addr\[2\] 0000 5 -reg_addr\[1\] 0000 6 -reg_addr\[0\] 0000 7 -reg_be 0000 10 -reg_wdata\[7\] 0000 11 -reg_wdata\[6\] 0000 12 -reg_wdata\[5\] 0000 13 -reg_wdata\[4\] 0000 14 -reg_wdata\[3\] 0000 15 -reg_wdata\[2\] 0000 16 -reg_wdata\[1\] 0000 17 -reg_wdata\[0\] 0000 18 -reg_rdata\[7\] 0000 19 -reg_rdata\[6\] 0000 20 -reg_rdata\[5\] 0000 21 -reg_rdata\[4\] 0000 22 -reg_rdata\[3\] 0000 23 -reg_rdata\[2\] 0000 24 -reg_rdata\[1\] 0000 25 -reg_rdata\[0\] 0000 26 -reg_ack 0000 27
diff --git a/openlane/uart/sta.tcl b/openlane/uart/sta.tcl deleted file mode 100644 index e9d4a77..0000000 --- a/openlane/uart/sta.tcl +++ /dev/null
@@ -1,56 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - -set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib" -set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib" -set ::env(CURRENT_NETLIST) /project/openlane/uart/runs/uart/results/lvs/uart_core.lvs.powered.v -set ::env(DESIGN_NAME) "uart_core" -set ::env(CURRENT_SPEF) /project/openlane/uart/runs/uart/results/routing/uart_core.spef -set ::env(BASE_SDC_FILE) "/project/openlane/uart/base.sdc" -set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8" -set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CAP_LOAD) "17.65" -set ::env(WIRE_RC_LAYER) "met1" - - -set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um -read_liberty -min $::env(LIB_FASTEST) -read_liberty -max $::env(LIB_SLOWEST) -read_verilog $::env(CURRENT_NETLIST) -link_design $::env(DESIGN_NAME) - -read_spef $::env(CURRENT_SPEF) - -read_sdc -echo $::env(BASE_SDC_FILE) - -# check for missing constraints -#check_setup -verbose > unconstraints.rpt - -set_operating_conditions -analysis_type bc_wc -# Propgate the clock -set_propagated_clock [all_clocks] - -report_tns -report_wns -report_power -report_checks -unique -slack_max -0.0 -group_count 100 -report_checks -unique -slack_min -0.0 -group_count 100 -report_checks -path_delay min_max -report_checks -group_count 100 -slack_max -0.01 - - - -
diff --git a/openlane/uart_i2cm/base.sdc b/openlane/uart_i2cm/base.sdc deleted file mode 100644 index 5a0d2fe..0000000 --- a/openlane/uart_i2cm/base.sdc +++ /dev/null
@@ -1,74 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - - -set_units -time ns -set ::env(CORE_CLOCK_PERIOD) "10" -set ::env(CORE_CLOCK_PORT) "app_clk" -set ::env(CORE_CLOCK_NAME) "app_clk" - -set ::env(LINE_CLOCK_PERIOD) "100" -set ::env(LINE_CLOCK_PORT) "u_lineclk_buf/X" -set ::env(LINE_CLOCK_NAME) "line_clk" - -###################################### -# WB Clock domain input output -###################################### -create_clock [get_ports $::env(CORE_CLOCK_PORT)] -name $::env(CORE_CLOCK_NAME) -period $::env(CORE_CLOCK_PERIOD) -create_clock [get_pins $::env(LINE_CLOCK_PORT)] -name $::env(LINE_CLOCK_NAME) -period $::env(LINE_CLOCK_PERIOD) - -set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6] -set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6] - -set line_input_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6] -set line_output_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6] -puts "\[INFO\]: Setting wb output delay to:$core_output_delay_value" -puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value" - - -set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_rstn} -set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {i2c_rstn} -set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {uart_i2c_sel} - -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*] -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*] -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wr*] -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_be*] -set_input_delay $core_input_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wdata*] - - -set_output_delay $core_output_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_rdata*] -set_output_delay $core_output_delay_value -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_ack*] - -set_input_delay $line_input_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_in*] -set_output_delay $line_input_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_oeb*] -set_output_delay $line_output_delay_value -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_out*] - - -set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(LINE_CLOCK_NAME)] - -set_clock_uncertainty -from $::env(CORE_CLOCK_NAME) -to $::env(CORE_CLOCK_NAME) -setup 0.400 -set_clock_uncertainty -from $::env(LINE_CLOCK_NAME) -to $::env(LINE_CLOCK_NAME) -setup 0.400 - -set_clock_uncertainty -from $::env(CORE_CLOCK_NAME) -to $::env(CORE_CLOCK_NAME) -hold 0.050 -set_clock_uncertainty -from $::env(LINE_CLOCK_NAME) -to $::env(LINE_CLOCK_NAME) -hold 0.050 - -# TODO set this as parameter -set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] -set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] -puts "\[INFO\]: Setting load to: $cap_load" -set_load $cap_load [all_outputs] -
diff --git a/openlane/uart_i2cm/config.tcl b/openlane/uart_i2cm/config.tcl deleted file mode 100644 index 088a579..0000000 --- a/openlane/uart_i2cm/config.tcl +++ /dev/null
@@ -1,95 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - -# Global -# ------ - -set script_dir [file dirname [file normalize [info script]]] -# Name -set ::env(DESIGN_NAME) uart_i2c_top - - -set ::env(DESIGN_IS_CORE) "0" -set ::env(FP_PDN_CORE_RING) "0" - -# Timing configuration -set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "app_clk" - -set ::env(SYNTH_MAX_FANOUT) 4 - -# Sources -# ------- - -# Local sources + no2usb sources -set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/uart/src/uart_core.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \ - $script_dir/../../verilog/rtl/lib/async_fifo_th.sv \ - $script_dir/../../verilog/rtl/lib/reset_sync.sv \ - $script_dir/../../verilog/rtl/lib/double_sync_low.v \ - $script_dir/../../verilog/rtl/lib/clk_ctl.v \ - $script_dir/../../verilog/rtl/lib/registers.v \ - $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v \ - $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v \ - $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v \ - $script_dir/../../verilog/rtl/uart_i2c/src/uart_i2c_top.sv \ - " - -set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes ] - -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" - -set ::env(LEC_ENABLE) 0 - -set ::env(VDD_PIN) [list {vccd1}] -set ::env(GND_PIN) [list {vssd1}] - - -# Floorplanning -# ------------- - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg -set ::env(FP_SIZING) "absolute" -set ::env(DIE_AREA) [list 0.0 0.0 300.0 400.0] - - - -# If you're going to use multiple power domains, then keep this disabled. -set ::env(RUN_CVC) 0 - -#set ::env(PDN_CFG) $script_dir/pdn.tcl - - -set ::env(PL_ROUTABILITY_DRIVEN) 1 - -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 - - -set ::env(GLB_RT_MAXLAYER) 4 -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 - -set ::env(DIODE_INSERTION_STRATEGY) 4 - -set ::env(FP_PDN_VPITCH) 100 -set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/uart_i2cm/pdn.tcl b/openlane/uart_i2cm/pdn.tcl deleted file mode 100644 index 1fe689b..0000000 --- a/openlane/uart_i2cm/pdn.tcl +++ /dev/null
@@ -1,49 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -# Power nets -set ::power_nets $::env(VDD_PIN) -set ::ground_nets $::env(GND_PIN) - -set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5" - -pdngen::specify_grid stdcell { - name grid - rails { - met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} - } - straps { - met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} - met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} - } - connect {{met1 met4} {met4 met5}} -} - -pdngen::specify_grid macro { - power_pins "VPWR" - ground_pins "VGND" - blockages "li1 met1 met2 met3 met4" - straps { - } - connect {{met4_PIN_ver met5}} -} - -set ::halo 5 - -# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area -set ::rails_start_with "POWER" ; - -# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area -set ::stripes_start_with "POWER" ;
diff --git a/openlane/uart_i2cm/pin_order.cfg b/openlane/uart_i2cm/pin_order.cfg deleted file mode 100644 index 870fa34..0000000 --- a/openlane/uart_i2cm/pin_order.cfg +++ /dev/null
@@ -1,40 +0,0 @@ -#BUS_SORT -#MANUAL_PLACE - -#S -app_clk 0000 0 -uart_rstn -i2c_rstn -uart_i2c_sel -io_in\[1\] -io_out\[1\] -io_oeb\[1\] -io_in\[0\] -io_out\[0\] -io_oeb\[0\] - -#N -reg_cs 0000 0 -reg_wr 0000 1 -reg_addr\[3\] 0000 4 -reg_addr\[2\] 0000 5 -reg_addr\[1\] 0000 6 -reg_addr\[0\] 0000 7 -reg_be 0000 10 -reg_wdata\[7\] 0000 11 -reg_wdata\[6\] 0000 12 -reg_wdata\[5\] 0000 13 -reg_wdata\[4\] 0000 14 -reg_wdata\[3\] 0000 15 -reg_wdata\[2\] 0000 16 -reg_wdata\[1\] 0000 17 -reg_wdata\[0\] 0000 18 -reg_rdata\[7\] 0000 19 -reg_rdata\[6\] 0000 20 -reg_rdata\[5\] 0000 21 -reg_rdata\[4\] 0000 22 -reg_rdata\[3\] 0000 23 -reg_rdata\[2\] 0000 24 -reg_rdata\[1\] 0000 25 -reg_rdata\[0\] 0000 26 -reg_ack 0000 27
diff --git a/openlane/uart_i2cm/sta.tcl b/openlane/uart_i2cm/sta.tcl deleted file mode 100644 index ef1ab52..0000000 --- a/openlane/uart_i2cm/sta.tcl +++ /dev/null
@@ -1,56 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - -set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib" -set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib" -set ::env(CURRENT_NETLIST) /project/openlane/uart_i2cm/runs/uart_i2cm/results/lvs/uart_i2c_top.lvs.powered.v -set ::env(DESIGN_NAME) "uart_i2c_top" -set ::env(CURRENT_SPEF) /project/openlane/uart_i2cm/runs/uart_i2cm/results/routing/uart_i2c_top.spef -set ::env(BASE_SDC_FILE) "/project/openlane/uart_i2cm/base.sdc" -set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8" -set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CAP_LOAD) "17.65" -set ::env(WIRE_RC_LAYER) "met1" - - -set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um -read_liberty -min $::env(LIB_FASTEST) -read_liberty -max $::env(LIB_SLOWEST) -read_verilog $::env(CURRENT_NETLIST) -link_design $::env(DESIGN_NAME) - -read_spef $::env(CURRENT_SPEF) - -read_sdc -echo $::env(BASE_SDC_FILE) - -# check for missing constraints -#check_setup -verbose > unconstraints.rpt - -set_operating_conditions -analysis_type bc_wc -# Propgate the clock -set_propagated_clock [all_clocks] - -report_tns -report_wns -report_power -report_checks -unique -slack_max -0.0 -group_count 100 -report_checks -unique -slack_min -0.0 -group_count 100 -report_checks -path_delay min_max -report_checks -group_count 100 -slack_max -0.01 - - - -
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl deleted file mode 100644 index 2fe0330..0000000 --- a/openlane/yifive/config.tcl +++ /dev/null
@@ -1,121 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -# Base Configurations. Don't Touch -# section begin -set script_dir [file dirname [file normalize [info script]]] - -source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl - -set ::env(DESIGN_NAME) yifive -set verilog_root $script_dir/../../verilog/ -set lef_root $script_dir/../../lef/ -set gds_root $script_dir/../../gds/ -#section end - -# User Configurations -# -set ::env(DESIGN_IS_CORE) 1 -set ::env(FP_PDN_CORE_RING) 1 - - -## Source Verilog Files -set ::env(VERILOG_FILES) "\ - $script_dir/../../caravel/verilog/rtl/defines.v \ - $script_dir/yifive.v" - -## Clock configurations -set ::env(CLOCK_PORT) "user_clock2 wb_clk_i" -#set ::env(CLOCK_NET) "mprj.clk" - -set ::env(CLOCK_PERIOD) "10" - -## Internal Macros -### Macro Placement -set ::env(FP_SIZING) "absolute" -set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg - -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" - - -### Black-box verilog and views -set ::env(VERILOG_FILES_BLACKBOX) "\ - $script_dir/../../verilog/gl/spi_master.v \ - $script_dir/../../verilog/gl/wb_interconnect.v \ - $script_dir/../../verilog/gl/glbl_cfg.v \ - $script_dir/../../verilog/gl/uart.v \ - $script_dir/../../verilog/gl/sdram.v \ - $script_dir/../../verilog/gl/wb_host.v \ - $script_dir/../../verilog/gl/clk_skew_adjust.v \ - $script_dir/../../verilog/gl/syntacore.v \ - " - -set ::env(EXTRA_LEFS) "\ - $lef_root/spi_master.lef \ - $lef_root/glbl_cfg.lef \ - $lef_root/wb_interconnect.lef \ - $lef_root/sdram.lef \ - $lef_root/uart.lef \ - $lef_root/wb_host.lef \ - $lef_root/clk_skew_adjust.lef \ - $lef_root/syntacore.lef \ - " - -set ::env(EXTRA_GDS_FILES) "\ - $gds_root/spi_master.gds \ - $gds_root/glbl_cfg.gds \ - $gds_root/wb_interconnect.gds \ - $gds_root/uart.gds \ - $gds_root/sdram.gds \ - $gds_root/wb_host.gds \ - $gds_root/clk_skew_adjust.gds \ - $gds_root/syntacore.gds \ - " - -set ::env(SYNTH_DEFINES) [list SYNTHESIS ] - -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ] - -set ::env(GLB_RT_MAXLAYER) 5 - -set ::env(FP_PDN_CHECK_NODES) 0 - -set ::env(RUN_KLAYOUT_DRC) 0 - -set ::env(VDD_PIN) [list {vccd1}] -set ::env(GND_PIN) [list {vssd1}] - - -# The following is because there are no std cells in the example wrapper project. -#set ::env(SYNTH_TOP_LEVEL) 1 -set ::env(PL_RANDOM_GLB_PLACEMENT) 1 - -set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 -set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 -set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0 -set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 -# -set ::env(DIODE_INSERTION_STRATEGY) 0 -set ::env(FILL_INSERTION) 0 -set ::env(TAP_DECAP_INSERTION) 0 -set ::env(CLOCK_TREE_SYNTH) 0 - -#set ::env(MAGIC_EXT_USE_GDS) "1" - - -set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250" - -
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg deleted file mode 100644 index 90cde69..0000000 --- a/openlane/yifive/pin_order.cfg +++ /dev/null
@@ -1,156 +0,0 @@ -#BUS_SORT -#NR -analog_io\[8\] -io_in\[15\] -io_out\[15\] -io_oeb\[15\] -analog_io\[9\] -io_in\[16\] -io_out\[16\] -io_oeb\[16\] -analog_io\[10\] -io_in\[17\] -io_out\[17\] -io_oeb\[17\] -analog_io\[11\] -io_in\[18\] -io_out\[18\] -io_oeb\[18\] -analog_io\[12\] -io_in\[19\] -io_out\[19\] -io_oeb\[19\] -analog_io\[13\] -io_in\[20\] -io_out\[20\] -io_oeb\[20\] -analog_io\[14\] -io_in\[21\] -io_out\[21\] -io_oeb\[21\] -analog_io\[15\] -io_in\[22\] -io_out\[22\] -io_oeb\[22\] -analog_io\[16\] -io_in\[23\] -io_out\[23\] -io_oeb\[23\] - -#S -wb_.* -wbs_.* -la_.* -user_clock2 -user_irq.* - -#E -io_in\[0\] -io_out\[0\] -io_oeb\[0\] -io_in\[1\] -io_out\[1\] -io_oeb\[1\] -io_in\[2\] -io_out\[2\] -io_oeb\[2\] -io_in\[3\] -io_out\[3\] -io_oeb\[3\] -io_in\[4\] -io_out\[4\] -io_oeb\[4\] -io_in\[5\] -io_out\[5\] -io_oeb\[5\] -io_in\[6\] -io_out\[6\] -io_oeb\[6\] -analog_io\[0\] -io_in\[7\] -io_out\[7\] -io_oeb\[7\] -analog_io\[1\] -io_in\[8\] -io_out\[8\] -io_oeb\[8\] -analog_io\[2\] -io_in\[9\] -io_out\[9\] -io_oeb\[9\] -analog_io\[3\] -io_in\[10\] -io_out\[10\] -io_oeb\[10\] -analog_io\[4\] -io_in\[11\] -io_out\[11\] -io_oeb\[11\] -analog_io\[5\] -io_in\[12\] -io_out\[12\] -io_oeb\[12\] -analog_io\[6\] -io_in\[13\] -io_out\[13\] -io_oeb\[13\] -analog_io\[7\] -io_in\[14\] -io_out\[14\] -io_oeb\[14\] - -#WR -analog_io\[17\] -io_in\[24\] -io_out\[24\] -io_oeb\[24\] -analog_io\[18\] -io_in\[25\] -io_out\[25\] -io_oeb\[25\] -analog_io\[19\] -io_in\[26\] -io_out\[26\] -io_oeb\[26\] -analog_io\[20\] -io_in\[27\] -io_out\[27\] -io_oeb\[27\] -analog_io\[21\] -io_in\[28\] -io_out\[28\] -io_oeb\[28\] -analog_io\[22\] -io_in\[29\] -io_out\[29\] -io_oeb\[29\] -analog_io\[23\] -io_in\[30\] -io_out\[30\] -io_oeb\[30\] -analog_io\[24\] -io_in\[31\] -io_out\[31\] -io_oeb\[31\] -analog_io\[25\] -io_in\[32\] -io_out\[32\] -io_oeb\[32\] -analog_io\[26\] -io_in\[33\] -io_out\[33\] -io_oeb\[33\] -analog_io\[27\] -io_in\[34\] -io_out\[34\] -io_oeb\[34\] -analog_io\[28\] -io_in\[35\] -io_out\[35\] -io_oeb\[35\] -io_in\[36\] -io_out\[36\] -io_oeb\[36\] -io_in\[37\] -io_out\[37\] -io_oeb\[37\]