| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h35m28s,0h27m5s,29668.888888888887,1.8,14834.444444444443,20,1125.28,26702,0,0,0,0,0,0,0,69,0,0,0,1591280,222490,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1348931410,0.0,19.87,15.65,3.42,0.14,-1,26588,26826,2335,2573,0,0,0,26702,508,0,693,1900,3881,2188,1037,6599,2386,2349,100,866,22835,255,23956,20.0,50.0,50,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,4,3 |
