openlane/syntacore/pin_order.cfg

#BUS_SORT

#MANUAL_PLACE
#E
core_clk            0000 0
rtc_clk             0000 1
cpu_rst_n           0000 2
irq_lines\[15\]     0000 3
irq_lines\[14\]     0000 4
irq_lines\[13\]     0000 5
irq_lines\[12\]     0000 6
irq_lines\[11\]     0000 7
irq_lines\[10\]     0000 8
irq_lines\[9\]     0000 9
irq_lines\[8\]     0000 10
irq_lines\[7\]     0000 11
irq_lines\[6\]     0000 12
irq_lines\[5\]     0000 13
irq_lines\[4\]     0000 14
irq_lines\[3\]     0000 15
irq_lines\[2\]     0000 16
irq_lines\[1\]     0000 17
irq_lines\[0\]     0000 18
soft_irq           0000 19
fuse_mhartid\[31\] 0000 20
fuse_mhartid\[30\] 0000 21
fuse_mhartid\[29\] 0000 22
fuse_mhartid\[28\] 0000 23
fuse_mhartid\[27\] 0000 24
fuse_mhartid\[26\] 0000 25
fuse_mhartid\[25\] 0000 26
fuse_mhartid\[24\] 0000 27
fuse_mhartid\[23\] 0000 28
fuse_mhartid\[22\] 0000 29
fuse_mhartid\[21\] 0000 30
fuse_mhartid\[20\] 0000 31
fuse_mhartid\[19\] 0000 32
fuse_mhartid\[18\] 0000 33
fuse_mhartid\[17\] 0000 34
fuse_mhartid\[16\] 0000 35
fuse_mhartid\[15\] 0000 36
fuse_mhartid\[14\] 0000 37
fuse_mhartid\[13\] 0000 38
fuse_mhartid\[12\] 0000 39
fuse_mhartid\[11\] 0000 40
fuse_mhartid\[10\] 0000 41
fuse_mhartid\[9\] 0000 42
fuse_mhartid\[8\] 0000 43
fuse_mhartid\[7\] 0000 44
fuse_mhartid\[6\] 0000 45
fuse_mhartid\[5\] 0000 46
fuse_mhartid\[4\] 0000 47
fuse_mhartid\[3\] 0000 48
fuse_mhartid\[2\] 0000 49
fuse_mhartid\[1\] 0000 50
fuse_mhartid\[0\] 0000 51

#W
wb_clk            0000 0
wb_rst_n          0000 1
pwrup_rst_n       0000 2
rst_n             0000 3
test_mode         0000 4
test_rst_n        0000 5

#N
wbd_imem_stb_o    0000 0
wbd_imem_we_o     0000 1
wbd_imem_adr_o\[31\]    0000 2
wbd_imem_adr_o\[30\]    0000 3
wbd_imem_adr_o\[29\]    0000 4
wbd_imem_adr_o\[28\]    0000 5
wbd_imem_adr_o\[27\]    0000 6
wbd_imem_adr_o\[26\]    0000 7
wbd_imem_adr_o\[25\]    0000 8
wbd_imem_adr_o\[24\]    0000 9
wbd_imem_adr_o\[23\]    0000 10
wbd_imem_adr_o\[22\]    0000 11
wbd_imem_adr_o\[21\]    0000 12
wbd_imem_adr_o\[20\]    0000 13
wbd_imem_adr_o\[19\]    0000 14
wbd_imem_adr_o\[18\]    0000 15
wbd_imem_adr_o\[17\]    0000 16
wbd_imem_adr_o\[16\]    0000 17
wbd_imem_adr_o\[15\]    0000 18
wbd_imem_adr_o\[14\]    0000 19
wbd_imem_adr_o\[13\]    0000 20
wbd_imem_adr_o\[12\]    0000 21
wbd_imem_adr_o\[11\]    0000 22
wbd_imem_adr_o\[10\]    0000 23
wbd_imem_adr_o\[9\]    0000 24
wbd_imem_adr_o\[8\]    0000 25
wbd_imem_adr_o\[7\]    0000 26
wbd_imem_adr_o\[6\]    0000 27
wbd_imem_adr_o\[5\]    0000 28
wbd_imem_adr_o\[4\]    0000 29
wbd_imem_adr_o\[3\]    0000 30
wbd_imem_adr_o\[2\]    0000 31
wbd_imem_adr_o\[1\]    0000 32
wbd_imem_adr_o\[0\]    0000 33
wbd_imem_sel_o\[3\]    0000 34
wbd_imem_sel_o\[2\]    0000 35
wbd_imem_sel_o\[1\]    0000 36
wbd_imem_sel_o\[0\]    0000 37
wbd_imem_dat_o\[31\]   0000 38
wbd_imem_dat_o\[30\]   0000 39
wbd_imem_dat_o\[29\]   0000 40
wbd_imem_dat_o\[28\]   0000 41
wbd_imem_dat_o\[27\]   0000 42
wbd_imem_dat_o\[26\]   0000 43
wbd_imem_dat_o\[25\]   0000 44
wbd_imem_dat_o\[24\]   0000 45
wbd_imem_dat_o\[23\]   0000 46
wbd_imem_dat_o\[22\]   0000 47
wbd_imem_dat_o\[21\]   0000 48
wbd_imem_dat_o\[20\]   0000 49
wbd_imem_dat_o\[19\]   0000 50
wbd_imem_dat_o\[18\]   0000 51
wbd_imem_dat_o\[17\]   0000 52
wbd_imem_dat_o\[16\]   0000 53
wbd_imem_dat_o\[15\]   0000 54
wbd_imem_dat_o\[14\]   0000 55
wbd_imem_dat_o\[13\]   0000 56
wbd_imem_dat_o\[12\]   0000 57
wbd_imem_dat_o\[11\]   0000 58
wbd_imem_dat_o\[10\]   0000 59
wbd_imem_dat_o\[9\]   0000 60
wbd_imem_dat_o\[8\]   0000 61
wbd_imem_dat_o\[7\]   0000 62
wbd_imem_dat_o\[6\]   0000 63
wbd_imem_dat_o\[5\]   0000 64
wbd_imem_dat_o\[4\]   0000 65
wbd_imem_dat_o\[3\]   0000 66
wbd_imem_dat_o\[2\]   0000 67
wbd_imem_dat_o\[1\]   0000 68
wbd_imem_dat_o\[0\]   0000 69
wbd_imem_dat_i\[31\]  0000 70
wbd_imem_dat_i\[30\]  0000 71
wbd_imem_dat_i\[29\]  0000 72
wbd_imem_dat_i\[28\]  0000 73
wbd_imem_dat_i\[27\]  0000 74
wbd_imem_dat_i\[26\]  0000 75
wbd_imem_dat_i\[25\]  0000 76
wbd_imem_dat_i\[24\]  0000 77
wbd_imem_dat_i\[23\]  0000 78
wbd_imem_dat_i\[22\]  0000 79
wbd_imem_dat_i\[21\]  0000 80
wbd_imem_dat_i\[20\]  0000 81
wbd_imem_dat_i\[19\]  0000 82
wbd_imem_dat_i\[18\]  0000 83
wbd_imem_dat_i\[17\]  0000 84
wbd_imem_dat_i\[16\]  0000 85
wbd_imem_dat_i\[15\]  0000 86
wbd_imem_dat_i\[14\]  0000 87
wbd_imem_dat_i\[13\]  0000 88
wbd_imem_dat_i\[12\]  0000 89
wbd_imem_dat_i\[11\]  0000 90
wbd_imem_dat_i\[10\]  0000 91
wbd_imem_dat_i\[9\]  0000 92
wbd_imem_dat_i\[8\]  0000 93
wbd_imem_dat_i\[7\]  0000 94
wbd_imem_dat_i\[6\]  0000 95
wbd_imem_dat_i\[5\]  0000 96
wbd_imem_dat_i\[4\]  0000 97
wbd_imem_dat_i\[3\]  0000 98
wbd_imem_dat_i\[2\]  0000 99
wbd_imem_dat_i\[1\]  0000 100
wbd_imem_dat_i\[0\]  0000 101
wbd_imem_ack_i       0000 102
wbd_imem_err_i       0000 103

wbd_dmem_stb_o       0500 0
wbd_dmem_we_o        0500 1
wbd_dmem_adr_o\[31\] 0500 2
wbd_dmem_adr_o\[30\] 0500 3
wbd_dmem_adr_o\[29\] 0500 4
wbd_dmem_adr_o\[28\] 0500 5
wbd_dmem_adr_o\[27\] 0500 6
wbd_dmem_adr_o\[26\] 0500 7
wbd_dmem_adr_o\[25\] 0500 8
wbd_dmem_adr_o\[24\] 0500 9
wbd_dmem_adr_o\[23\] 0500 10
wbd_dmem_adr_o\[22\] 0500 11
wbd_dmem_adr_o\[21\] 0500 12
wbd_dmem_adr_o\[20\] 0500 13
wbd_dmem_adr_o\[19\] 0500 14
wbd_dmem_adr_o\[18\] 0500 15
wbd_dmem_adr_o\[17\] 0500 16
wbd_dmem_adr_o\[16\] 0500 17
wbd_dmem_adr_o\[15\] 0500 18
wbd_dmem_adr_o\[14\] 0500 19
wbd_dmem_adr_o\[13\] 0500 20
wbd_dmem_adr_o\[12\] 0500 21
wbd_dmem_adr_o\[11\] 0500 22
wbd_dmem_adr_o\[10\] 0500 23
wbd_dmem_adr_o\[9\] 0500 24
wbd_dmem_adr_o\[8\] 0500 25
wbd_dmem_adr_o\[7\] 0500 26
wbd_dmem_adr_o\[6\] 0500 27
wbd_dmem_adr_o\[5\] 0500 28
wbd_dmem_adr_o\[4\] 0500 29
wbd_dmem_adr_o\[3\] 0500 30
wbd_dmem_adr_o\[2\] 0500 31
wbd_dmem_adr_o\[1\] 0500 32
wbd_dmem_adr_o\[0\] 0500 33
wbd_dmem_sel_o\[3\]  0500 34
wbd_dmem_sel_o\[2\]  0500 35
wbd_dmem_sel_o\[1\]  0500 36
wbd_dmem_sel_o\[0\]  0500 37
wbd_dmem_dat_o\[31\] 0500 38
wbd_dmem_dat_o\[30\] 0500 39
wbd_dmem_dat_o\[29\] 0500 40
wbd_dmem_dat_o\[28\] 0500 41
wbd_dmem_dat_o\[27\] 0500 42
wbd_dmem_dat_o\[26\] 0500 43
wbd_dmem_dat_o\[25\] 0500 44
wbd_dmem_dat_o\[24\] 0500 45
wbd_dmem_dat_o\[23\] 0500 46
wbd_dmem_dat_o\[22\] 0500 47
wbd_dmem_dat_o\[21\] 0500 48
wbd_dmem_dat_o\[20\] 0500 49
wbd_dmem_dat_o\[19\] 0500 50
wbd_dmem_dat_o\[18\] 0500 51
wbd_dmem_dat_o\[17\] 0500 52
wbd_dmem_dat_o\[16\] 0500 53
wbd_dmem_dat_o\[15\] 0500 54
wbd_dmem_dat_o\[14\] 0500 55
wbd_dmem_dat_o\[13\] 0500 56
wbd_dmem_dat_o\[12\] 0500 57
wbd_dmem_dat_o\[11\] 0500 58
wbd_dmem_dat_o\[10\] 0500 59
wbd_dmem_dat_o\[9\] 0500 60
wbd_dmem_dat_o\[8\] 0500 61
wbd_dmem_dat_o\[7\] 0500 62
wbd_dmem_dat_o\[6\] 0500 63
wbd_dmem_dat_o\[5\] 0500 64
wbd_dmem_dat_o\[4\] 0500 65
wbd_dmem_dat_o\[3\] 0500 66
wbd_dmem_dat_o\[2\] 0500 67
wbd_dmem_dat_o\[1\] 0500 68
wbd_dmem_dat_o\[0\] 0500 69
wbd_dmem_dat_i\[31\] 0500 70
wbd_dmem_dat_i\[30\] 0500 71
wbd_dmem_dat_i\[29\] 0500 72
wbd_dmem_dat_i\[28\] 0500 73
wbd_dmem_dat_i\[27\] 0500 74
wbd_dmem_dat_i\[26\] 0500 75
wbd_dmem_dat_i\[25\] 0500 76
wbd_dmem_dat_i\[24\] 0500 77
wbd_dmem_dat_i\[23\] 0500 78
wbd_dmem_dat_i\[22\] 0500 79
wbd_dmem_dat_i\[21\] 0500 80
wbd_dmem_dat_i\[20\] 0500 81
wbd_dmem_dat_i\[19\] 0500 82
wbd_dmem_dat_i\[18\] 0500 83
wbd_dmem_dat_i\[17\] 0500 84
wbd_dmem_dat_i\[16\] 0500 85
wbd_dmem_dat_i\[15\] 0500 86
wbd_dmem_dat_i\[14\] 0500 87
wbd_dmem_dat_i\[13\] 0500 88
wbd_dmem_dat_i\[12\] 0500 89
wbd_dmem_dat_i\[11\] 0500 90
wbd_dmem_dat_i\[10\] 0500 91
wbd_dmem_dat_i\[9\] 0500 92
wbd_dmem_dat_i\[8\] 0500 93
wbd_dmem_dat_i\[7\] 0500 94
wbd_dmem_dat_i\[6\] 0500 95
wbd_dmem_dat_i\[5\] 0500 96
wbd_dmem_dat_i\[4\] 0500 97
wbd_dmem_dat_i\[3\] 0500 98
wbd_dmem_dat_i\[2\] 0500 99
wbd_dmem_dat_i\[1\] 0500 100
wbd_dmem_dat_i\[0\] 0500 101
wbd_dmem_ack_i      0500 102
wbd_dmem_err_i      0500 103