riscv compliace submodule are removed to pass mpw-3 documentation precheck
diff --git a/.gitmodules b/.gitmodules index 7fc7971..03d7cd9 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -1,15 +1,3 @@ -[submodule "verilog/rtl/syntacore/scr1/dependencies/riscv-tests"] - path = verilog/rtl/syntacore/scr1/dependencies/riscv-tests - url = https://github.com/riscv/riscv-tests - branch = e30978a71921159aec38eeefd848fca4ed39a826 -[submodule "verilog/rtl/syntacore/scr1/dependencies/riscv-compliance"] - path = verilog/rtl/syntacore/scr1/dependencies/riscv-compliance - url = https://github.com/riscv/riscv-compliance - branch = d51259b2a949be3af02e776c39e135402675ac9b -[submodule "verilog/rtl/syntacore/scr1/dependencies/coremark"] - path = verilog/rtl/syntacore/scr1/dependencies/coremark - url = https://github.com/eembc/coremark - branch = 7f420b6bdbff436810ef75381059944e2b0d79e8 [submodule "caravel1"] path = caravel url = https://github.com/efabless/caravel-lite.git
diff --git a/verilog/rtl/syntacore/scr1/dependencies/coremark b/verilog/rtl/syntacore/scr1/dependencies/coremark deleted file mode 160000 index 7f420b6..0000000 --- a/verilog/rtl/syntacore/scr1/dependencies/coremark +++ /dev/null
@@ -1 +0,0 @@ -Subproject commit 7f420b6bdbff436810ef75381059944e2b0d79e8
diff --git a/verilog/rtl/syntacore/scr1/dependencies/riscv-compliance b/verilog/rtl/syntacore/scr1/dependencies/riscv-compliance deleted file mode 160000 index d51259b..0000000 --- a/verilog/rtl/syntacore/scr1/dependencies/riscv-compliance +++ /dev/null
@@ -1 +0,0 @@ -Subproject commit d51259b2a949be3af02e776c39e135402675ac9b
diff --git a/verilog/rtl/syntacore/scr1/dependencies/riscv-tests b/verilog/rtl/syntacore/scr1/dependencies/riscv-tests deleted file mode 160000 index e30978a..0000000 --- a/verilog/rtl/syntacore/scr1/dependencies/riscv-tests +++ /dev/null
@@ -1 +0,0 @@ -Subproject commit e30978a71921159aec38eeefd848fca4ed39a826