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### RISC V core customization YiFive SOC
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1.Source code Update : Modified some of the system verilog syntax to basic verilog syntax to compile/synthesis in open source tool like simulator (iverilog) and synthesis (yosys).
2.Source code modification: Modified the AXI/AHB interface to wishbone interface towards instruction & data memory interface
+```
## 8bit SDRAM Controller
Due to number of pin limitation in carvel shuttle, YiFive SOC integrate 8bit SDRAM controller.
