Waveform dump command added
diff --git a/Makefile b/Makefile
index f898ec3..f82551b 100644
--- a/Makefile
+++ b/Makefile
@@ -43,7 +43,7 @@
.PHONY: verify
verify:
cd ./verilog/dv/ && \
- export SIM=${SIM} && \
+ export SIM=${SIM} DUMP=${DUMP} && \
$(MAKE) -j$(THREADS)
# Install DV setup
@@ -55,8 +55,9 @@
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
TARGET_PATH=$(shell pwd)
PDK_PATH=${PDK_ROOT}/sky130A
-VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make"
$(DV_PATTERNS): verify-% : ./verilog/dv/%
+# PDK ROOT is not defined, then use pdk from docker at opt/riscv_64
@if [ ! -d "$(PDK_ROOT)" ]; then \
docker run -v ${TARGET_PATH}:${TARGET_PATH} \
-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
@@ -77,7 +78,7 @@
BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
.PHONY: $(BLOCKS)
$(BLOCKS): %:
- cd openlane && $(MAKE) $*
+ export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
# Install caravel
.PHONY: install
@@ -189,3 +190,4 @@
help:
cd $(CARAVEL_ROOT) && $(MAKE) help
@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
diff --git a/signoff/glbl_cfg/OPENLANE_VERSION b/signoff/glbl_cfg/OPENLANE_VERSION
index ad796aa..bab6e84 100644
--- a/signoff/glbl_cfg/OPENLANE_VERSION
+++ b/signoff/glbl_cfg/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-6-gbc3b032
+openlane v0.21-9-g94fe743
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index 68bccb3..4b70572 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h15m36s,0h9m28s,45883.33333333334,0.12,22941.66666666667,40,569.11,2753,0,0,0,0,0,0,0,0,0,-1,0,131923,23407,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,25.3,27.26,0.31,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h8m53s,0h4m39s,45883.33333333334,0.12,22941.66666666667,40,569.06,2753,0,0,0,0,0,0,0,0,0,-1,0,131923,23407,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,25.3,27.26,0.31,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/verilog/dv/model/mt48lc8m8a2.v b/verilog/dv/model/mt48lc8m8a2.v
index cf309f1..1d82cba 100755
--- a/verilog/dv/model/mt48lc8m8a2.v
+++ b/verilog/dv/model/mt48lc8m8a2.v
@@ -571,17 +571,17 @@
if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD))
begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time);
end
if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD))
begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time);
end
if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD))
begin
- //->tb.test_control.error_detected;
+ ->error_detected;
$display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time);
end
// Read Command
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index dcb19ed..c52a974 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -44,6 +44,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
@@ -63,6 +64,7 @@
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -70,6 +72,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 1958002..e637dbe 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -182,13 +182,13 @@
#TARGETS += isr_sample
# Comment this target if you don't want to run the coremark
-TARGETS += coremark
+#TARGETS += coremark
# Comment this target if you don't want to run the dhrystone
#TARGETS += dhrystone21
# Comment this target if you don't want to run the hello test
-#TARGETS += hello
+TARGETS += hello
# Targets
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 089a877..39da3b4 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -45,6 +45,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
@@ -64,6 +65,7 @@
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -71,6 +73,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index c01b1ed..fa32693 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -45,6 +45,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
@@ -64,6 +65,7 @@
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
rm crt_tcm.o user_risc_boot.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -71,6 +73,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_spi/Makefile
index bc48c2a..054ec11 100644
--- a/verilog/dv/user_spi/Makefile
+++ b/verilog/dv/user_spi/Makefile
@@ -45,6 +45,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
@@ -64,6 +65,7 @@
${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump
rm crt_tcm.o user_risc_boot.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -71,6 +73,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 0e4b390..fa0a9cf 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -45,6 +45,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
@@ -64,6 +65,7 @@
${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
rm crt_tcm.o user_uart.o
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
@@ -71,6 +73,15 @@
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index c0cd3d8..aecb8cf 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -40,6 +40,7 @@
## Simulation mode: RTL/GL
SIM?=RTL
+DUMP?=OFF
.SUFFIXES:
@@ -53,12 +54,21 @@
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-I $(UPRJ_INCLUDE_PATH4) \
$< -o $@
+ else
+ iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+ -I $(UPRJ_INCLUDE_PATH4) \
+ $< -o $@
+ endif
else
iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
diff --git a/verilog/rtl/syntacore/scr1/dependencies/riscv-compliance b/verilog/rtl/syntacore/scr1/dependencies/riscv-compliance
index 9141cf9..d51259b 160000
--- a/verilog/rtl/syntacore/scr1/dependencies/riscv-compliance
+++ b/verilog/rtl/syntacore/scr1/dependencies/riscv-compliance
@@ -1 +1 @@
-Subproject commit 9141cf9274b610d059199e8aa2e21f54a0bc6a6e
+Subproject commit d51259b2a949be3af02e776c39e135402675ac9b
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
index cb87b13..1cdc5c4 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
@@ -59,7 +59,8 @@
*(sc_test_section)
. = ALIGN(CL_SIZE);
PROVIDE(__TEXT_END__ = .);
- } >ROM
+ } >RAM AT>ROM
+
.rodata ALIGN(CL_SIZE) : {
__global_pointer$ = . + 0x800;
@@ -67,7 +68,7 @@
. = ALIGN(CL_SIZE);
LONG(0x13);
. = ALIGN(CL_SIZE);
- } >ROM
+ } >RAM AT>ROM
/* data segment */
