| ############################################################################### |
| # Created by write_sdc |
| # Sat Nov 13 06:42:06 2021 |
| ############################################################################### |
| current_design uart_i2c_usb_top |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name app_clk -period 10.0000 [get_ports {app_clk}] |
| create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf/X}] |
| create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}] |
| set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -setup 0.2000 |
| set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -hold 0.1000 |
| set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -setup 0.2000 |
| set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -hold 0.1000 |
| set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -setup 0.2000 |
| set_clock_groups -name async_clock -asynchronous \ |
| -group [get_clocks {app_clk}]\ |
| -group [get_clocks {line_clk}]\ |
| -group [get_clocks {usb_clk}] -comment {Async Clock group} |
| set_input_delay 0.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {i2c_rstn}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {i2c_rstn}] |
| set_input_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_in[0]}] |
| set_input_delay 60.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_in[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_in[1]}] |
| set_input_delay 60.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_in[1]}] |
| |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_cs}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_cs}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wr}] |
| set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wr}] |
| set_input_delay 0.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {uart_rstn}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {uart_rstn}] |
| set_input_delay 0.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {usb_rstn}] |
| set_input_delay 2.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {usb_rstn}] |
| set_output_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_oeb[0]}] |
| set_output_delay 60.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_oeb[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_oeb[1]}] |
| set_output_delay 60.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_oeb[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_out[0]}] |
| set_output_delay 40.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_out[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_out[1]}] |
| set_output_delay 40.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_out[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_ack}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_ack}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[10]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[11]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[12]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[13]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[14]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[15]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[16]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[17]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[18]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[19]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[20]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[21]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[22]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[23]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[24]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[25]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[26]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[27]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[28]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[29]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[2]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[30]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[31]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[3]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[4]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[5]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[6]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[7]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[8]}] |
| set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[9]}] |
| set_multicycle_path -hold\ |
| -from [list [get_ports {reg_cs}]\ |
| [get_ports {reg_wr}]]\ |
| -to [get_ports {reg_ack}] 1 |
| set_multicycle_path -setup\ |
| -from [list [get_ports {reg_cs}]\ |
| [get_ports {reg_wr}]]\ |
| -to [get_ports {reg_ack}] 2 |
| set_max_delay\ |
| -from [list [get_ports {uart_i2c_usb_sel[0]}]\ |
| [get_ports {uart_i2c_usb_sel[1]}]] 10.0000 |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {reg_ack}] |
| set_load -pin_load 0.0334 [get_ports {wbd_clk_uart}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_oeb[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_out[0]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {app_clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2c_rstn}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rstn}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_clk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_rstn}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_i2c_usb_sel[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_i2c_usb_sel[0]}] |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |