commit b41301c44e5c308dde8a8fcd7cdb391922950e8e
author manarabdelaty <manarabdelatty@aucegypt.edu> Mon Apr 19 23:30:35 2021 +0200
committer manarabdelaty <manarabdelatty@aucegypt.edu> Mon Apr 19 23:30:35 2021 +0200
tree f0fda3977a6a4cd7ed332d209b85d7530176567a
parent 5e23de794767e02c25850a5c4cbc136f830d31f7

Added top level makefile

openlane/user_proj_example/config.tcl

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 4ea25c6..0de7a65 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -18,7 +18,7 @@
 set ::env(DESIGN_NAME) user_proj_example
 
 set ::env(VERILOG_FILES) "\
-	$script_dir/../../caravel/verilog/rtl/defines.v \
+	$script_dir/../../caravel-lite/verilog/rtl/defines.v \
 	$script_dir/../../verilog/rtl/user_proj_example.v"
 
 set ::env(CLOCK_PORT) ""