Added top level makefile
diff --git a/openlane/Makefile b/openlane/Makefile
index f242a3c..aad81ae 120000
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -1 +1 @@
-caravel-lite/openlane/Makefile
\ No newline at end of file
+/home/ma/ef/caravel_project_example/caravel-lite/openlane/Makefile
\ No newline at end of file
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 4ea25c6..0de7a65 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -18,7 +18,7 @@
set ::env(DESIGN_NAME) user_proj_example
set ::env(VERILOG_FILES) "\
- $script_dir/../../caravel/verilog/rtl/defines.v \
+ $script_dir/../../caravel-lite/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_proj_example.v"
set ::env(CLOCK_PORT) ""
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 82814d4..cf90dec 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -26,7 +26,7 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
- $script_dir/../../caravel/verilog/rtl/defines.v \
+ $script_dir/../../caravel-lite/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
index 5e924e2..ae292ce 120000
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -1 +1 @@
-caravel-lite/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
+/home/ma/ef/caravel_project_example/caravel-lite/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
