| /root/fault_tolerant_16-bit_alu_design/Makefile |
| /root/fault_tolerant_16-bit_alu_design/docs/environment.yml |
| /root/fault_tolerant_16-bit_alu_design/docs/Makefile |
| /root/fault_tolerant_16-bit_alu_design/docs/source/index.rst |
| /root/fault_tolerant_16-bit_alu_design/docs/source/conf.py |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/Makefile |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/la_test2_tb.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/la_test2.c |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/Makefile |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/la_test1.c |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/Makefile |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/la_test1_tb.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/Makefile |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/io_ports_tb.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/io_ports.c |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/mprj_stimulus/Makefile |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/mprj_stimulus/mprj_stimulus.c |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/wb_port/wb_port_tb.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/wb_port/Makefile |
| /root/fault_tolerant_16-bit_alu_design/verilog/dv/wb_port/wb_port.c |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/ALU_Opt.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/RPA_4bit.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/F_Adder.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/booth_16bit_sign.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/ALU_opt_2.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/KP_Voter.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/RP_Add_Sub_4bit.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/uprj_netlists.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/ALU_opt_3.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/constraint.sdc |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/to_ALU_opt_TMR_KP_Voter.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/H_Adder.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/user_proj_example.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/user_project_wrapper.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/SIPO.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/RPA_16bit.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/MUX_2X1.v |
| /root/fault_tolerant_16-bit_alu_design/verilog/rtl/booth_recoder.v |
| /root/fault_tolerant_16-bit_alu_design/openlane/Makefile |
| /root/fault_tolerant_16-bit_alu_design/openlane/user_proj_example/config.json |
| /root/fault_tolerant_16-bit_alu_design/openlane/user_proj_example/config.tcl |
| /root/fault_tolerant_16-bit_alu_design/openlane/user_project_wrapper/config.json |
| /root/fault_tolerant_16-bit_alu_design/openlane/user_project_wrapper/config.tcl |
