jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/logs/precheck.log - third_party/shuttle/sky130/mpw-004/slot-023 - Git at Google

 2022-01-02 15:06:01 - [INFO] - {{Project Git Info}} Repository: https://github.com/SultanShadow/RAD_HARD_ALU.git | Branch: main | Commit: 6c92fdf2c9f9ce6fb92ce2bf7359652cee053eb7
 2022-01-02 15:06:01 - [INFO] - {{INSTALLING CARAVEL}} Running `make install` in fault_tolerant_16-bit_alu_design
 2022-01-02 15:06:09 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: fault_tolerant_16-bit_alu_design
 2022-01-02 15:06:13 - [INFO] - {{Project GDS Info}} user_project_wrapper: f87422c67250383706db84c3a2550fb6b1f4f184
 2022-01-02 15:06:13 - [INFO] - {{Tools Info}} KLayout: v0.27.5 | Magic: v8.3.245
 2022-01-02 15:06:13 - [INFO] - {{PDKs Info}} Open PDKs: 476f7428f7f686de51a5164c702629a9b9f2da46 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 2022-01-02 15:06:13 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'fault_tolerant_16-bit_alu_design/jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/logs'
 2022-01-02 15:06:13 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
 2022-01-02 15:06:13 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
 2022-01-02 15:06:14 - [INFO] - An approved LICENSE (Apache-2.0) was found in fault_tolerant_16-bit_alu_design.
 2022-01-02 15:06:14 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
 2022-01-02 15:06:15 - [INFO] - An approved LICENSE (Apache-2.0) was found in fault_tolerant_16-bit_alu_design.
 2022-01-02 15:06:16 - [INFO] - An approved LICENSE (Apache-2.0) was found in fault_tolerant_16-bit_alu_design.
 2022-01-02 15:06:16 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
 2022-01-02 15:06:16 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (fault_tolerant_16-bit_alu_design/verilog/rtl/generate_pp_cv.v): 'utf-8' codec can't decode byte 0x92 in position 2972: invalid start byte
 2022-01-02 15:06:16 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 44 non-compliant file(s) with the SPDX Standard.
 2022-01-02 15:06:16 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['fault_tolerant_16-bit_alu_design/Makefile', 'fault_tolerant_16-bit_alu_design/docs/environment.yml', 'fault_tolerant_16-bit_alu_design/docs/Makefile', 'fault_tolerant_16-bit_alu_design/docs/source/index.rst', 'fault_tolerant_16-bit_alu_design/docs/source/conf.py', 'fault_tolerant_16-bit_alu_design/verilog/dv/Makefile', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/la_test2_tb.v', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/la_test2.c', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/Makefile', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/la_test1.c', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/Makefile', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/la_test1_tb.v', 'fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/Makefile', 'fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/io_ports_tb.v', 'fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/io_ports.c']
 2022-01-02 15:06:16 - [INFO] - For the full SPDX compliance report check: fault_tolerant_16-bit_alu_design/jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/logs/spdx_compliance_report.log
 2022-01-02 15:06:16 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
 2022-01-02 15:06:16 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
 2022-01-02 15:06:16 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
 2022-01-02 15:06:16 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
 2022-01-02 15:06:17 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
 2022-01-02 15:06:17 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
 2022-01-02 15:06:17 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
 2022-01-02 15:06:17 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
 2022-01-02 15:06:17 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_project_wrapper.v
 2022-01-02 15:06:17 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_project_wrapper.v
 2022-01-02 15:06:17 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
 2022-01-02 15:06:17 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
 2022-01-02 15:06:21 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel.
 2022-01-02 15:06:21 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances).
 2022-01-02 15:06:21 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
 2022-01-02 15:06:21 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
 2022-01-02 15:06:22 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
 2022-01-02 15:06:22 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
 2022-01-02 15:06:22 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
 2022-01-02 15:06:22 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (1 instances).
 2022-01-02 15:06:22 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
 2022-01-02 15:06:22 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
 2022-01-02 15:06:22 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
 2022-01-02 15:06:22 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
 2022-01-02 15:06:22 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
 2022-01-02 15:06:22 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
 2022-01-02 15:06:22 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
 2022-01-02 15:06:22 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_project_wrapper_empty.gds.gz
 2022-01-02 15:06:22 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_project_wrapper_empty.gds.gz
 2022-01-02 15:06:26 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view fault_tolerant_16-bit_alu_design/jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/outputs/user_project_wrapper.xor.gds
 2022-01-02 15:06:26 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
 2022-01-02 15:06:26 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
 2022-01-02 15:06:45 - [INFO] - 0 DRC violations
 2022-01-02 15:06:45 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2022-01-02 15:06:45 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
 2022-01-02 15:06:49 - [INFO] - No DRC Violations found
 2022-01-02 15:06:49 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2022-01-02 15:06:49 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
 2022-01-02 15:07:20 - [INFO] - No DRC Violations found
 2022-01-02 15:07:20 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2022-01-02 15:07:20 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
 2022-01-02 15:07:27 - [INFO] - No DRC Violations found
 2022-01-02 15:07:27 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2022-01-02 15:07:27 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
 2022-01-02 15:07:30 - [INFO] - No DRC Violations found
 2022-01-02 15:07:30 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2022-01-02 15:07:30 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
 2022-01-02 15:07:33 - [INFO] - No DRC Violations found
 2022-01-02 15:07:33 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2022-01-02 15:07:33 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
 2022-01-02 15:07:34 - [INFO] - No DRC Violations found
 2022-01-02 15:07:34 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
 2022-01-02 15:07:34 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'fault_tolerant_16-bit_alu_design/jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/logs'
 2022-01-02 15:07:34 - [INFO] - {{SUCCESS}} All Checks Passed !!!
	2022-01-02 15:06:01 - [INFO] - {{Project Git Info}} Repository: https://github.com/SultanShadow/RAD_HARD_ALU.git \| Branch: main \| Commit: 6c92fdf2c9f9ce6fb92ce2bf7359652cee053eb7
	2022-01-02 15:06:01 - [INFO] - {{INSTALLING CARAVEL}} Running `make install` in fault_tolerant_16-bit_alu_design
	2022-01-02 15:06:09 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: fault_tolerant_16-bit_alu_design
	2022-01-02 15:06:13 - [INFO] - {{Project GDS Info}} user_project_wrapper: f87422c67250383706db84c3a2550fb6b1f4f184
	2022-01-02 15:06:13 - [INFO] - {{Tools Info}} KLayout: v0.27.5 \| Magic: v8.3.245
	2022-01-02 15:06:13 - [INFO] - {{PDKs Info}} Open PDKs: 476f7428f7f686de51a5164c702629a9b9f2da46 \| Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
	2022-01-02 15:06:13 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'fault_tolerant_16-bit_alu_design/jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/logs'
	2022-01-02 15:06:13 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
	2022-01-02 15:06:13 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
	2022-01-02 15:06:14 - [INFO] - An approved LICENSE (Apache-2.0) was found in fault_tolerant_16-bit_alu_design.
	2022-01-02 15:06:14 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
	2022-01-02 15:06:15 - [INFO] - An approved LICENSE (Apache-2.0) was found in fault_tolerant_16-bit_alu_design.
	2022-01-02 15:06:16 - [INFO] - An approved LICENSE (Apache-2.0) was found in fault_tolerant_16-bit_alu_design.
	2022-01-02 15:06:16 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
	2022-01-02 15:06:16 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (fault_tolerant_16-bit_alu_design/verilog/rtl/generate_pp_cv.v): 'utf-8' codec can't decode byte 0x92 in position 2972: invalid start byte
	2022-01-02 15:06:16 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 44 non-compliant file(s) with the SPDX Standard.
	2022-01-02 15:06:16 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['fault_tolerant_16-bit_alu_design/Makefile', 'fault_tolerant_16-bit_alu_design/docs/environment.yml', 'fault_tolerant_16-bit_alu_design/docs/Makefile', 'fault_tolerant_16-bit_alu_design/docs/source/index.rst', 'fault_tolerant_16-bit_alu_design/docs/source/conf.py', 'fault_tolerant_16-bit_alu_design/verilog/dv/Makefile', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/la_test2_tb.v', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/la_test2.c', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test2/Makefile', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/la_test1.c', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/Makefile', 'fault_tolerant_16-bit_alu_design/verilog/dv/la_test1/la_test1_tb.v', 'fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/Makefile', 'fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/io_ports_tb.v', 'fault_tolerant_16-bit_alu_design/verilog/dv/io_ports/io_ports.c']
	2022-01-02 15:06:16 - [INFO] - For the full SPDX compliance report check: fault_tolerant_16-bit_alu_design/jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/logs/spdx_compliance_report.log
	2022-01-02 15:06:16 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
	2022-01-02 15:06:16 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
	2022-01-02 15:06:16 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
	2022-01-02 15:06:16 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
	2022-01-02 15:06:17 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
	2022-01-02 15:06:17 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
	2022-01-02 15:06:17 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
	2022-01-02 15:06:17 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
	2022-01-02 15:06:17 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_project_wrapper.v
	2022-01-02 15:06:17 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_project_wrapper.v
	2022-01-02 15:06:17 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
	2022-01-02 15:06:17 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
	2022-01-02 15:06:21 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel.
	2022-01-02 15:06:21 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances).
	2022-01-02 15:06:21 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
	2022-01-02 15:06:21 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
	2022-01-02 15:06:22 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
	2022-01-02 15:06:22 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
	2022-01-02 15:06:22 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
	2022-01-02 15:06:22 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (1 instances).
	2022-01-02 15:06:22 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
	2022-01-02 15:06:22 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
	2022-01-02 15:06:22 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
	2022-01-02 15:06:22 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
	2022-01-02 15:06:22 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
	2022-01-02 15:06:22 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
	2022-01-02 15:06:22 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
	2022-01-02 15:06:22 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_project_wrapper_empty.gds.gz
	2022-01-02 15:06:22 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_project_wrapper_empty.gds.gz
	2022-01-02 15:06:26 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view fault_tolerant_16-bit_alu_design/jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/outputs/user_project_wrapper.xor.gds
	2022-01-02 15:06:26 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
	2022-01-02 15:06:26 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
	2022-01-02 15:06:45 - [INFO] - 0 DRC violations
	2022-01-02 15:06:45 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2022-01-02 15:06:45 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
	2022-01-02 15:06:49 - [INFO] - No DRC Violations found
	2022-01-02 15:06:49 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2022-01-02 15:06:49 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
	2022-01-02 15:07:20 - [INFO] - No DRC Violations found
	2022-01-02 15:07:20 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2022-01-02 15:07:20 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
	2022-01-02 15:07:27 - [INFO] - No DRC Violations found
	2022-01-02 15:07:27 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2022-01-02 15:07:27 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
	2022-01-02 15:07:30 - [INFO] - No DRC Violations found
	2022-01-02 15:07:30 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2022-01-02 15:07:30 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
	2022-01-02 15:07:33 - [INFO] - No DRC Violations found
	2022-01-02 15:07:33 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2022-01-02 15:07:33 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
	2022-01-02 15:07:34 - [INFO] - No DRC Violations found
	2022-01-02 15:07:34 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
	2022-01-02 15:07:34 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'fault_tolerant_16-bit_alu_design/jobs/mpw_precheck/87493039-5021-4cd7-aba1-e7403d5cb6b3/logs'
	2022-01-02 15:07:34 - [INFO] - {{SUCCESS}} All Checks Passed !!!