update
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 272f64e..8a62505 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
index d209e27..9f68565 100644
--- a/verilog/rtl/user_analog_project_wrapper.v
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -126,20 +126,20 @@
top_wrapper top_wrapper_0 (
//rram_LUT2 mprj (
-// `ifdef USE_POWER_PINS
-// .vdda1(vdda1), // User area 1 3.3V power
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1), // User area 1 3.3V power
// .vdda2(vdda2), // User area 2 3.3V power
// .vssa1(vssa1), // User area 1 analog ground
// .vssa2(vssa2), // User area 2 analog ground
-// .vccd1(vccd1), // User area 1 1.8V power
+ .vccd1(vccd1), // User area 1 1.8V power
// .vccd2(vccd2), // User area 2 1.8V power
-// .vssd1(vssd1), // User area 1 digital ground
+ .vssd1(vssd1), // User area 1 digital ground
// .vssd2(vssd2), // User area 2 digital ground
-// `endif
+ `endif
- .vccd1(vccd1), // User area 1 1.8V power
- .vdda1(vdda1), // User area 1 1.8V power
- .vssd1(vssd1), // User area 1 digital ground
+// .vccd1(vccd1), // User area 1 1.8V power
+// .vdda1(vdda1), // User area 1 1.8V power
+// .vssd1(vssd1), // User area 1 digital ground
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
