all standalone components
diff --git a/gds/and.ext b/gds/and.ext new file mode 100644 index 0000000..25d194d --- /dev/null +++ b/gds/and.ext
@@ -0,0 +1,56 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +port "Z1" 6 30 -470 210 -420 li +port "gnd!" 8 438 -726 438 -726 li +port "GND" 1 -110 -840 590 -770 m4 +port "OUT" 3 530 -240 670 -190 li +port "B" 5 90 -210 210 -170 li +port "B" 5 90 -210 120 -120 m1 +port "B" 5 -170 -120 120 -90 m1 +port "A" 4 -170 -210 -40 -170 li +port "vdd!" 9 428 810 428 810 li +port "out1" 7 280 -220 460 -180 li +port "VDD" 2 -170 880 670 940 nw +node "Z1" 1640 305.275 30 -470 li 0 0 0 0 0 0 0 0 64000 1920 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59000 1900 0 0 0 0 0 0 0 0 0 0 0 0 +node "gnd!" 1568 1223.21 438 -726 li 0 0 0 0 0 0 0 0 56000 1720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65000 2340 12800 640 20000 800 28800 960 62400 1780 0 0 0 0 +equiv "gnd!" "GND" +node "OUT" 2627 624.887 530 -240 li 0 0 0 0 0 0 0 0 24000 760 60800 1680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98200 3260 0 0 0 0 0 0 0 0 0 0 0 0 +node "B" 2102 596.73 -170 -120 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46300 2880 0 0 8800 440 16000 960 0 0 0 0 0 0 0 0 0 0 +node "A" 2103 442.645 -170 -210 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46300 2880 0 0 9200 460 0 0 0 0 0 0 0 0 0 0 0 0 +node "vdd!" 5769 1998 428 810 li 0 0 0 0 0 0 0 0 0 0 144000 4080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 149400 4940 19200 960 30000 1200 30000 1200 93600 3080 0 0 0 0 +node "out1" 6488 1253.5 280 -220 li 0 0 0 0 0 0 0 0 32000 960 83200 2400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3340 0 0 136500 4640 0 0 0 0 0 0 0 0 0 0 0 0 +node "VDD" 1983 2469.6 -170 880 nw 0 0 0 0 823200 3640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "w_n126_n696#" 0 0 -126 -696 pw 310384 2388 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "gnd!" "Z1" 409.78 +cap "OUT" "Z1" 43.6452 +cap "OUT" "gnd!" 198 +cap "B" "Z1" 67.1786 +cap "A" "gnd!" 57.75 +cap "B" "OUT" 8.8 +cap "vdd!" "Z1" 7.96552 +cap "out1" "Z1" 356.371 +cap "vdd!" "gnd!" 13.8886 +cap "out1" "gnd!" 226.769 +cap "vdd!" "OUT" 574.768 +cap "A" "B" 87.6201 +cap "out1" "OUT" 261.752 +cap "vdd!" "B" 13.5882 +cap "vdd!" "A" 13.5882 +cap "VDD" "OUT" 2.3125 +cap "out1" "B" 176.792 +cap "out1" "A" 13.5179 +cap "out1" "vdd!" 1441.54 +cap "VDD" "vdd!" 48.86 +cap "VDD" "out1" 6.1975 +device msubckt sky130_fd_pr__nfet_01v8 480 -670 481 -669 l=30 w=300 "w_n126_n696#" "out1" 60 0 "gnd!" 300 0 "OUT" 300 0 +device msubckt sky130_fd_pr__nfet_01v8 230 -670 231 -669 l=30 w=400 "w_n126_n696#" "B" 60 0 "Z1" 400 0 "out1" 400 0 +device msubckt sky130_fd_pr__nfet_01v8 -20 -670 -19 -669 l=30 w=400 "w_n126_n696#" "A" 60 0 "gnd!" 400 0 "Z1" 400 0 +device msubckt sky130_fd_pr__pfet_01v8 480 20 481 21 l=30 w=760 "VDD" "out1" 60 0 "vdd!" 760 0 "OUT" 760 0 +device msubckt sky130_fd_pr__pfet_01v8 230 20 231 21 l=30 w=520 "VDD" "B" 60 0 "vdd!" 520 0 "out1" 520 0 +device msubckt sky130_fd_pr__pfet_01v8 -20 20 -19 21 l=30 w=520 "VDD" "A" 60 0 "vdd!" 520 0 "out1" 520 0
diff --git a/gds/and_pd.ext b/gds/and_pd.ext new file mode 100644 index 0000000..bef37a2 --- /dev/null +++ b/gds/and_pd.ext
@@ -0,0 +1,51 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +port "Z1" 3 130 -400 190 -360 li +port "GND" 2 -100 -620 670 -550 m4 +port "Out" 5 570 -230 670 -190 li +port "Out1" 4 320 -230 520 -190 li +port "B" 7 -100 -120 20 -90 m1 +port "A" 6 -100 -230 0 -190 li +port "VDD" 1 -100 410 670 470 nw +node "Z1" 964 189.22 130 -400 li 0 0 0 0 0 0 0 0 28800 1040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27600 1040 0 0 0 0 0 0 0 0 0 0 0 0 +node "GND" 1039 1185.71 -100 -620 m4 0 0 0 0 0 0 0 0 28800 1040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38800 1560 12800 640 20000 800 20000 800 84100 2400 0 0 0 0 +node "Out" 1335 380.525 570 -230 li 0 0 0 0 0 0 0 0 14400 520 28800 880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52800 1880 0 0 0 0 0 0 0 0 0 0 0 0 +node "a_n60_n30#" 3907 1640.44 -60 -30 pdif 0 0 0 0 0 0 0 0 0 0 86400 2640 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 88800 3240 19200 960 30000 1200 30000 1200 82600 2460 0 0 0 0 +node "Out1" 4193 982.6 320 -230 li 0 0 0 0 0 0 0 0 14400 520 57600 1760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 1960 0 0 97200 3500 0 0 0 0 0 0 0 0 0 0 0 0 +node "B" 1340 513.855 -100 -120 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 1960 0 0 6400 320 18100 1100 0 0 0 0 0 0 0 0 0 0 +node "A" 1358 374.675 -100 -230 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 1960 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0 +node "VDD" 2352 1494 -100 410 nw 0 0 0 0 498000 2860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "w_n86_n496#" 0 0 -86 -496 pw 172144 1948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "GND" "Z1" 192.37 +cap "Out" "Z1" 19.8 +cap "Out" "GND" 118.8 +cap "a_n60_n30#" "Z1" 8.88462 +cap "Out1" "Z1" 178.758 +cap "a_n60_n30#" "GND" 17.7692 +cap "Out1" "GND" 176.55 +cap "B" "Z1" 57.75 +cap "a_n60_n30#" "Out" 277.2 +cap "Out1" "Out" 188.1 +cap "B" "Out" 8.8 +cap "A" "GND" 57.75 +cap "Out1" "a_n60_n30#" 1023.37 +cap "B" "a_n60_n30#" 18.7 +cap "VDD" "Out" 1.85 +cap "B" "Out1" 271.254 +cap "A" "a_n60_n30#" 18.7 +cap "VDD" "a_n60_n30#" 37.17 +cap "A" "Out1" 13.5179 +cap "VDD" "Out1" 3.7 +cap "A" "B" 75.0211 +device msubckt sky130_fd_pr__nfet_01v8 520 -470 521 -469 l=30 w=180 "w_n86_n496#" "Out1" 60 0 "GND" 180 0 "Out" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 270 -470 271 -469 l=30 w=180 "w_n86_n496#" "B" 60 0 "Z1" 180 0 "Out1" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 20 -470 21 -469 l=30 w=180 "w_n86_n496#" "A" 60 0 "GND" 180 0 "Z1" 180 0 +device msubckt sky130_fd_pr__pfet_01v8 520 -30 521 -29 l=30 w=360 "VDD" "Out1" 60 0 "a_n60_n30#" 360 0 "Out" 360 0 +device msubckt sky130_fd_pr__pfet_01v8 270 -30 271 -29 l=30 w=360 "VDD" "B" 60 0 "a_n60_n30#" 360 0 "Out1" 360 0 +device msubckt sky130_fd_pr__pfet_01v8 20 -30 21 -29 l=30 w=360 "VDD" "A" 60 0 "a_n60_n30#" 360 0 "Out1" 360 0
diff --git a/gds/cbank.ext b/gds/cbank.ext new file mode 100644 index 0000000..b96a4ae --- /dev/null +++ b/gds/cbank.ext
@@ -0,0 +1,94 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +use switch switch_0 1 0 6830 0 1 -1308 +use switch switch_1 1 0 5810 0 1 -1308 +use switch switch_2 1 0 4830 0 1 -1308 +use switch switch_3 1 0 3850 0 1 -1308 +use switch switch_4 1 0 2900 0 1 -1308 +use switch switch_5 1 0 1890 0 1 -1308 +parameters sky130_fd_pr__cap_mim_m3_1 w=w l=l +port "a5" 8 6940 200 6940 200 li +port "a4" 7 5920 200 5920 200 li +port "a3" 6 4940 210 4940 210 li +port "a2" 4 3960 210 3960 210 li +port "a1" 3 3010 220 3010 220 li +port "a0" 2 2000 220 2000 220 li +port "v" 1 20 1360 20 1360 li +port "gnd!" 5 4950 -1370 4950 -1370 li +node "li_1720_n30#" 13 1589.34 1720 -30 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0 +node "a5" 85 44.6475 6940 200 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 700 160 0 0 0 0 0 0 0 0 0 0 0 0 +node "a4" 85 44.6475 5920 200 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 700 160 0 0 0 0 0 0 0 0 0 0 0 0 +node "a3" 85 44.6475 4940 210 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 700 160 0 0 0 0 0 0 0 0 0 0 0 0 +node "a2" 85 44.6475 3960 210 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 700 160 0 0 0 0 0 0 0 0 0 0 0 0 +node "a1" 85 44.6475 3010 220 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 700 160 0 0 0 0 0 0 0 0 0 0 0 0 +node "a0" 85 44.6475 2000 220 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 700 160 0 0 0 0 0 0 0 0 0 0 0 0 +node "v" 27 7164.56 20 1360 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37300 820 36100 760 36100 760 36100 760 4117898 30562 0 0 0 0 +node "a_6660_n30#" 133 1402.86 6660 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0 +node "a_5640_n30#" 133 1402.86 5640 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0 +node "a_4660_n30#" 133 1402.86 4660 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0 +node "a_3680_n30#" 133 1402.86 3680 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0 +node "a_2730_n30#" 133 1402.86 2730 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0 +node "a_1720_n30#" 120 0 1720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "gnd!" 0 0 4950 -1370 li 415872 7104 0 0 0 0 0 0 0 0 135200 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 512800 9000 433800 7420 496800 8120 1964400 12740 2795480 19244 0 0 0 0 +cap "a_2730_n30#" "li_1720_n30#" 199.5 +cap "a_1720_n30#" "li_1720_n30#" 18.13 +cap "a_6660_n30#" "v" 1301.39 +cap "a_5640_n30#" "v" 1301.39 +cap "a_5640_n30#" "a_6660_n30#" 191.52 +cap "a_4660_n30#" "v" 1301.39 +cap "a_3680_n30#" "v" 1301.39 +cap "a_4660_n30#" "a_5640_n30#" 199.5 +cap "a_2730_n30#" "v" 1301.39 +cap "a_3680_n30#" "a_4660_n30#" 199.5 +cap "a_2730_n30#" "a_3680_n30#" 199.5 +cap "v" "li_1720_n30#" 1301.39 +device csubckt sky130_fd_pr__cap_mim_m3_1 6510 590 6511 591 w=560 l=560 "None" "v" 1856 0 "a_6660_n30#" 1440 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 5510 590 5511 591 w=560 l=560 "None" "v" 1856 0 "a_5640_n30#" 1440 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 4520 590 4521 591 w=560 l=560 "None" "v" 1856 0 "a_4660_n30#" 1440 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 3530 590 3531 591 w=560 l=560 "None" "v" 1856 0 "a_3680_n30#" 1440 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 2540 590 2541 591 w=560 l=560 "None" "v" 1856 0 "a_2730_n30#" 1440 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 1550 590 1551 591 w=560 l=560 "None" "v" 1856 0 "li_1720_n30#" 1440 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 70 130 71 131 w=1040 l=1000 "None" "v" 3616 0 "gnd!" 1440 0 +cap "switch_4/vin" "switch_4/vout" -0.157143 +cap "a1" "switch_4/vin" -183.5 +cap "a0" "switch_5/vout" 4.23077 +cap "a0" "switch_5/vin" 83.635 +cap "a1" "switch_4/vout" 4.23077 +cap "a1" "switch_4/vin" 83.635 +cap "a2" "switch_3/vout" 4.23077 +cap "a2" "switch_3/vin" 83.635 +cap "switch_2/vout" "a3" 4.23077 +cap "switch_2/vin" "a3" 83.635 +cap "a5" "switch_0/vin" 83.635 +cap "a4" "switch_1/vout" 4.23077 +cap "a4" "switch_1/vin" 83.635 +cap "switch_0/vout" "a5" 4.23077 +merge "switch_0/vout" "switch_0/w_n216_n26#" -343.969 -1102432 -12828 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -280 -1316 0 0 0 0 0 0 -29100 -494 0 0 0 0 +merge "switch_0/w_n216_n26#" "switch_2/vout" +merge "switch_2/vout" "switch_2/w_n216_n26#" +merge "switch_2/w_n216_n26#" "switch_1/vout" +merge "switch_1/vout" "switch_1/w_n216_n26#" +merge "switch_1/w_n216_n26#" "switch_3/vout" +merge "switch_3/vout" "switch_3/w_n216_n26#" +merge "switch_3/w_n216_n26#" "switch_5/vout" +merge "switch_5/vout" "switch_4/vout" +merge "switch_4/vout" "switch_4/w_n216_n26#" +merge "switch_4/w_n216_n26#" "switch_5/w_n216_n26#" +merge "switch_5/w_n216_n26#" "gnd!" +merge "switch_1/vin" "a_5640_n30#" -684.59 0 0 0 0 0 0 0 0 -23520 -560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -23520 -560 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_5/vin" "li_1720_n30#" -1228.51 0 0 0 0 0 0 0 0 450840 -560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44964 -560 -366512 0 -716960 0 -214424 0 0 0 0 0 0 0 +merge "li_1720_n30#" "a_1720_n30#" +merge "switch_4/vin" "a_2730_n30#" -324.233 0 0 0 0 0 0 0 0 91460 -560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 91460 -560 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_0/vin" "a_6660_n30#" -807.245 0 0 0 0 0 0 0 0 -156120 -560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -156120 -560 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_3/vin" "a_3680_n30#" -1258.88 0 0 0 0 0 0 0 0 542680 -560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67480 -560 -366512 0 -716960 0 -232694 -223 0 0 0 0 0 0 +merge "switch_5/vcont" "a0" -38.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -140 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_4/vcont" "a1" -23.6075 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16100 -140 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_3/vcont" "a2" -24.255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15400 -140 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_2/vcont" "a3" -38.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -140 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_1/vcont" "a4" -16.485 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23800 -140 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_0/vcont" "a5" -35.91 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2800 -140 0 0 0 0 0 0 0 0 0 0 0 0 +merge "switch_2/vin" "a_4660_n30#" -523.275 0 0 0 0 0 0 0 0 108080 -560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 108080 -560 0 0 0 0 131950 0 0 0 0 0 0 0
diff --git a/gds/cp.ext b/gds/cp.ext index 1aa3c82..f84eca9 100644 --- a/gds/cp.ext +++ b/gds/cp.ext
@@ -26,23 +26,23 @@ node "upbar" 658 1347.77 6930 -320 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1444800 9060 0 0 126800 2040 0 0 0 0 0 0 0 0 0 0 0 0 node "vdd!" 18302 139352 4230 3990 li 0 0 0 0 43093400 28900 0 0 704700 10080 5472000 31840 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 745200 5020 0 0 5560800 43900 1430500 20260 818100 12540 818100 12540 6272200 36660 0 0 0 0 substrate "gnd!" 0 0 4280 -3300 li 16003824 41948 0 0 0 0 0 0 3419400 21800 243600 3420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1389600 8600 0 0 3637300 30060 802800 10020 421200 6360 421200 6360 4550400 19920 0 0 0 0 -cap "vdd!" "a_3060_n2840#" 320.4 -cap "vdd!" "a_7110_0#" 42.55 -cap "vdd!" "a_6370_0#" 402.828 -cap "vdd!" "a_3060_0#" 1788.27 -cap "vdd!" "a_1710_0#" 714.147 -cap "vdd!" "out" 376.075 -cap "vdd!" "a_1710_n2840#" 254.08 -cap "vdd!" "a_10_n50#" 530.297 -cap "vdd!" "upbar" 149.92 -cap "a_1710_0#" "down" 320.4 -cap "upbar" "down" 20.625 cap "a_10_n50#" "vbias" 192.9 -cap "out" "a_1710_0#" 841.733 -cap "a_1710_n2840#" "a_1710_0#" 828.847 -cap "a_10_n50#" "a_1710_0#" 41.6842 +cap "vdd!" "a_7110_0#" 42.55 +cap "vdd!" "a_3060_n2840#" 320.4 +cap "upbar" "down" 20.625 +cap "a_1710_0#" "down" 320.4 cap "a_1710_n2840#" "out" 606.81 +cap "out" "a_1710_0#" 841.733 +cap "vdd!" "out" 376.075 cap "upbar" "a_1710_n2840#" 291.6 +cap "a_1710_n2840#" "a_1710_0#" 828.847 +cap "vdd!" "a_1710_n2840#" 254.08 +cap "a_10_n50#" "a_1710_0#" 41.6842 +cap "vdd!" "a_6370_0#" 402.828 +cap "vdd!" "a_10_n50#" 530.297 +cap "vdd!" "a_3060_0#" 1788.27 +cap "vdd!" "upbar" 149.92 +cap "vdd!" "a_1710_0#" 714.147 device msubckt sky130_fd_pr__nfet_01v8 8100 -2840 8101 -2839 l=360 w=1800 "gnd!" "a_1710_0#" 720 0 "a_7110_n2840#" 1800 0 "out" 1800 0 device msubckt sky130_fd_pr__nfet_01v8 6750 -2840 6751 -2839 l=360 w=1800 "gnd!" "down" 720 0 "gnd!" 1800 0 "a_7110_n2840#" 1800 0 device msubckt sky130_fd_pr__nfet_01v8 5400 -2840 5401 -2839 l=360 w=1800 "gnd!" "out" 720 0 "a_3060_n2840#" 1800 0 "gnd!" 1800 0
diff --git a/gds/divider.ext b/gds/divider.ext new file mode 100644 index 0000000..cb767ce --- /dev/null +++ b/gds/divider.ext
@@ -0,0 +1,362 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +use nor nor_0 -1 0 6630 0 -1 3210 +use nor nor_1 -1 0 5660 0 -1 3210 +use and and_0 -1 0 4660 0 -1 2930 +use prescaler prescaler_0 1 0 50 0 1 400 +use tspc tspc_0 1 0 4120 0 1 990 +use tspc tspc_1 1 0 5700 0 1 990 +use tspc tspc_2 1 0 7280 0 1 990 +port "gnd" 1 5430 30 5620 90 m4 +port "gnd" 1 3830 30 4010 90 m4 +port "vdd" 2 5450 1860 5630 1920 m4 +port "vdd" 2 3990 1930 4830 1990 m4 +port "vdd" 2 5770 2160 6140 2220 m4 +port "vdd" 2 4700 2160 5170 2220 m4 +port "gnd" 1 3830 3700 4070 3770 m4 +port "gnd" 1 3770 3120 3830 3770 m4 +port "clk" 4 -370 860 -310 900 m2 +port "Out" 3 8660 820 8790 870 li +port "mc2" 5 -370 3580 450 3610 m2 +node "m4_7020_30#" 0 79.26 7020 30 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 480 0 0 0 0 +node "gnd" 0 83.08 5430 30 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11400 500 0 0 0 0 +node "gnd" 0 79.08 3830 30 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 480 0 0 0 0 +node "m4_7030_1860#" 0 89.6 7030 1860 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 480 0 0 0 0 +node "vdd" 0 78.66 5450 1860 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 480 0 0 0 0 +node "vdd" 1 312.48 3990 1930 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58800 1820 0 0 0 0 +node "vdd" 0 148 5770 2160 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22200 860 0 0 0 0 +node "vdd" 1 345.66 4700 2160 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52200 1860 0 0 0 0 +node "m4_5770_3730#" 0 163.54 5770 3730 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22200 860 0 0 0 0 +node "m4_4690_3730#" 0 209.38 4690 3730 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29400 1100 0 0 0 0 +node "gnd" 1 377.96 3770 3120 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60100 2040 0 0 0 0 +node "m2_3910_680#" 1 122.385 3910 680 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8200 580 0 0 0 0 0 0 0 0 +node "clk" 0 42.02 -370 860 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2400 200 0 0 0 0 0 0 0 0 +node "m1_5770_3360#" 16 1813.54 5770 3360 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105800 6840 38300 1960 0 0 0 0 0 0 0 0 +node "li_7140_680#" 43 3235 7140 680 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 226300 14980 0 0 0 0 0 0 0 0 0 0 +node "li_5560_680#" 24 1325.71 5560 680 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 91500 5960 0 0 0 0 0 0 0 0 0 0 +node "li_3980_680#" 25 1368.34 3980 680 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 94000 6160 0 0 0 0 0 0 0 0 0 0 +node "Out" 32 111.612 8660 820 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6500 360 0 0 0 0 0 0 0 0 0 0 0 0 +node "li_7040_820#" 13 214.937 7040 820 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 6400 320 11900 480 0 0 0 0 0 0 0 0 +node "li_5460_820#" 13 214.895 5460 820 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 6400 320 11800 480 0 0 0 0 0 0 0 0 +node "li_3310_1810#" 314 639.68 3310 1810 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 45100 2240 0 0 0 0 0 0 0 0 0 0 0 0 +node "li_5740_3250#" 25 1510.52 5740 3250 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 29300 1740 91000 5420 0 0 0 0 0 0 0 0 +node "li_6130_3350#" 19 802.775 6130 3350 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 55000 3560 0 0 0 0 0 0 0 0 0 0 +node "li_4830_3100#" 180 368.33 4830 3100 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23600 1260 0 0 0 0 0 0 0 0 0 0 0 0 +node "li_2870_2670#" 482 898.77 2870 2670 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63200 3240 0 0 0 0 0 0 0 0 0 0 0 0 +node "mc2" 155 3424.46 -370 3580 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16400 900 6400 320 225200 14700 0 0 0 0 0 0 0 0 +node "w_n140_1520#" 3438 3270.42 -140 1520 nw 0 0 0 0 1008000 4240 0 0 122500 1400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67080 1036 67080 1036 67080 1036 67080 1036 168928 2064 0 0 0 0 +node "w_2780_1920#" 31943 20273.1 2780 1920 nw 0 0 0 0 6485992 23000 0 0 245000 2800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134160 2072 134160 2072 134160 2072 134160 2072 610588 4880 0 0 0 0 +substrate "w_n966_n46#" 0 0 -966 -46 pw 2535060 32560 0 0 0 0 0 0 0 0 1757600 27040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9826000 57800 0 0 0 0 0 0 0 0 0 0 0 0 +cap "li_5740_3250#" "li_5560_680#" 21.9534 +cap "li_5740_3250#" "li_3980_680#" 22.5 +cap "mc2" "m1_5770_3360#" 35.7143 +cap "mc2" "li_7140_680#" 61.52 +cap "li_5740_3250#" "li_5460_820#" 128.305 +cap "w_2780_1920#" "m1_5770_3360#" 53.84 +cap "li_6130_3350#" "li_5740_3250#" 68.1032 +cap "mc2" "li_5740_3250#" 22.679 +cap "w_2780_1920#" "li_3310_1810#" 24.0375 +cap "w_2780_1920#" "li_5740_3250#" 72.945 +cap "w_2780_1920#" "li_6130_3350#" 7.215 +cap "w_2780_1920#" "li_2870_2670#" 76.8485 +cap "vdd" "vdd" 33.5 +cap "vdd" "vdd" 51.2353 +cap "vdd" "vdd" 20.1 +cap "li_5560_680#" "m4_7020_30#" 24.425 +cap "li_3980_680#" "gnd" 24.425 +cap "li_3980_680#" "gnd" 27.1625 +cap "li_5740_3250#" "vdd" 27.9 +cap "li_3310_1810#" "vdd" 35.39 +cap "li_5740_3250#" "vdd" 27.9 +cap "li_7140_680#" "m1_5770_3360#" 19.2857 +cap "li_5560_680#" "m1_5770_3360#" 16.875 +cap "li_5560_680#" "li_7140_680#" 437.5 +cap "w_2780_1920#" "m4_7030_1860#" 40.0711 +cap "w_2780_1920#" "vdd" 0.84 +cap "li_7040_820#" "m1_5770_3360#" 90 +cap "li_3980_680#" "li_5560_680#" 782.5 +cap "Out" "li_7140_680#" 23.5 +cap "w_2780_1920#" "vdd" 9.82 +cap "w_2780_1920#" "vdd" 4.08 +cap "li_7040_820#" "li_5560_680#" 15 +cap "w_2780_1920#" "vdd" 8.88 +cap "li_5740_3250#" "m1_5770_3360#" 286.375 +cap "mc2" "gnd" 27.9 +cap "li_5460_820#" "li_3980_680#" 20 +cap "li_6130_3350#" "m1_5770_3360#" 136.842 +cap "w_n966_n46#" "prescaler_0/nand_1/A" 17.3684 +cap "prescaler_0/nand_1/w_n46_n476#" "prescaler_0/GND" 21.945 +cap "prescaler_0/nand_1/w_n46_n476#" "prescaler_0/tspc_2/Z2" 27.6618 +cap "prescaler_0/tspc_2/a_630_n680#" "prescaler_0/nand_1/w_n46_n476#" 9.78378 +cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/a_630_n680#" 4.89189 +cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/Z2" 27.6618 +cap "prescaler_0/tspc_2/w_n146_n706#" "prescaler_0/tspc_1/GND" 30.14 +cap "tspc_0/Z4" "tspc_0/D" 35.0633 +cap "tspc_0/Z2" "tspc_0/D" 141.466 +cap "gnd" "tspc_0/D" 413.181 +cap "tspc_0/Z3" "tspc_0/D" 1.36364 +cap "tspc_0/Z2" "prescaler_0/tspc_1/w_n146_n706#" 27.6618 +cap "prescaler_0/tspc_1/a_630_n680#" "prescaler_0/tspc_1/w_n146_n706#" 4.89189 +cap "gnd" "prescaler_0/tspc_1/w_n146_n706#" 21.945 +cap "gnd" "tspc_0/w_n140_n70#" 0.12 +cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375 +cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985 +cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195 +cap "tspc_0/a_740_n680#" "tspc_0/Q" 145.525 +cap "tspc_0/Q" "tspc_1/D" 70.641 +cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065 +cap "tspc_1/w_n140_n70#" "tspc_0/Q" 5.55112e-17 +cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714 +cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823 +cap "tspc_0/a_740_n680#" "tspc_0/a_630_n680#" 159.583 +cap "tspc_1/Z4" "tspc_1/D" 33.0938 +cap "tspc_0/a_740_n680#" "gnd" 281.141 +cap "tspc_1/Z2" "tspc_1/D" 213.298 +cap "tspc_0/a_630_n680#" "tspc_1/D" 5.45455 +cap "gnd" "tspc_1/D" 346.096 +cap "tspc_1/Z4" "tspc_0/Q" 30.4615 +cap "tspc_1/Z2" "tspc_0/Q" 25.8231 +cap "gnd" "tspc_0/Q" 21.2143 +cap "w_n966_n46#" "tspc_1/Z2" 27.6618 +cap "w_n966_n46#" "tspc_0/a_630_n680#" 9.78378 +cap "w_n966_n46#" "gnd" 23.265 +cap "gnd" "tspc_1/Z2" 7.81579 +cap "gnd" "tspc_0/a_630_n680#" 7.61538 +cap "tspc_1/D" "tspc_1/Z3" 1.36364 +cap "tspc_0/a_740_n680#" "tspc_1/D" -7.31795 +cap "tspc_2/D" "tspc_1/GND" 339.551 +cap "w_n966_n46#" "tspc_2/Z2" 12.6176 +cap "tspc_1/GND" "tspc_2/Z2" 7.81579 +cap "tspc_1/a_740_n680#" "tspc_1/Q" 155.525 +cap "tspc_2/D" "tspc_2/Z3" 0.681818 +cap "tspc_2/D" "tspc_2/Z4" 20.0553 +cap "tspc_1/a_740_n680#" "tspc_2/w_n140_n70#" 0.065 +cap "tspc_2/D" "tspc_2/Z2" 309.898 +cap "tspc_1/a_740_n680#" "tspc_1/a_630_n680#" 159.107 +cap "tspc_1/Q" "tspc_1/GND" 21.2143 +cap "tspc_1/a_740_n680#" "tspc_1/GND" 440.385 +cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619 +cap "tspc_1/Q" "tspc_2/D" 70.641 +cap "w_n966_n46#" "tspc_1/GND" 30.14 +cap "w_n966_n46#" "tspc_1/a_630_n680#" 9.78378 +cap "tspc_1/Q" "tspc_2/Z4" 30.4615 +cap "tspc_1/a_740_n680#" "tspc_2/Z4" 10.5882 +cap "tspc_1/a_740_n680#" "tspc_2/Z2" 116.18 +cap "tspc_1/Q" "tspc_2/Z2" 25.8231 +cap "tspc_1/GND" "tspc_1/a_630_n680#" 7.61538 +cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622 +cap "tspc_2/a_630_n680#" "tspc_2/D" 159.583 +cap "tspc_2/GND" "tspc_2/D" 450.398 +cap "tspc_2/Z4" "tspc_2/D" 17.815 +cap "tspc_2/a_630_n680#" "tspc_1/w_n146_n706#" 9.78378 +cap "tspc_2/GND" "tspc_1/w_n146_n706#" 23.265 +cap "tspc_2/Z2" "tspc_1/w_n146_n706#" 15.0441 +cap "tspc_2/Z4" "li_5560_680#" 10.5882 +cap "Out" "tspc_2/D" 20.775 +cap "tspc_2/Z3" "tspc_2/D" 0.681818 +cap "tspc_2/D" "tspc_1/Q" -1.77636e-15 +cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 78.0797 +cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/A" 12.2938 +cap "w_n966_n46#" "prescaler_0/nand_1/A" 14.7632 +cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/OUT" -2.84217e-14 +cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/vdd!" 4.57853 +cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/Q" 6.67557 +cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_0/Q" 6.67557 +cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/Z2" -1.77636e-15 +cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 2.73 +cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/Z1" 3.19744e-14 +cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 73.8879 +cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/a_280_n230#" 16.0962 +cap "prescaler_0/tspc_1/Z3" "prescaler_0/nand_0/VDD" -2.37588e-14 +cap "prescaler_0/tspc_1/Z1" "prescaler_0/nand_0/VDD" 3.55271e-15 +cap "prescaler_0/tspc_1/Z2" "prescaler_0/nand_0/VDD" -4.61853e-14 +cap "vdd" "and_0/OUT" 7.5 +cap "vdd" "prescaler_0/mc1" 4.79032 +cap "vdd" "tspc_0/Z2" 10 +cap "vdd" "tspc_0/Z1" 8.88178e-14 +cap "vdd" "prescaler_0/tspc_1/Q" 19.25 +cap "vdd" "prescaler_0/GND" 244.839 +cap "vdd" "prescaler_0/tspc_1/a_740_n680#" 114.95 +cap "tspc_0/a_740_n680#" "tspc_1/Z2" 41.1927 +cap "nor_0/VDD" "vdd" -3.46 +cap "vdd" "tspc_0/Q" 93.7845 +cap "nor_0/VDD" "tspc_0/a_740_n680#" 4.63 +cap "vdd" "tspc_0/a_740_n680#" 177.528 +cap "tspc_0/a_740_n680#" "tspc_0/Q" 75.365 +cap "tspc_0/Q" "tspc_1/Z1" 7 +cap "nor_0/VDD" "vdd" 224.245 +cap "tspc_1/Q" "tspc_2/Z1" 7 +cap "tspc_1/a_740_n680#" "tspc_2/Z2" 85.1351 +cap "tspc_1/a_740_n680#" "tspc_1/Q" 75.365 +cap "nor_0/VDD" "tspc_2/Z2" 7.54952e-15 +cap "nor_0/VDD" "tspc_2/Z1" 2.25375e-14 +cap "nor_0/VDD" "tspc_1/Z3" -2.37588e-14 +cap "nor_0/VDD" "tspc_1/Q" 93.7845 +cap "nor_0/VDD" "tspc_1/Z2" -2.57572e-14 +cap "vdd" "tspc_1/a_740_n680#" 13.3333 +cap "nor_0/VDD" "tspc_1/a_740_n680#" 76.5957 +cap "tspc_2/Z1" "tspc_2/vdd!" -1.86517e-14 +cap "tspc_2/vdd!" "tspc_2/a_740_n680#" 13.125 +cap "tspc_2/Z3" "tspc_2/vdd!" -2.37588e-14 +cap "Out" "tspc_2/vdd!" 5.9508e-14 +cap "tspc_2/Z2" "tspc_2/vdd!" -2.13163e-14 +cap "prescaler_0/tspc_0/vdd!" "w_n140_1520#" 6.56545 +cap "w_n140_1520#" "prescaler_0/tspc_0/Q" 27.2014 +cap "prescaler_0/tspc_0/Z2" "prescaler_0/tspc_0/w_n146_n706#" 9.75806 +cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/Q" 9.57252 +cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/a_300_n150#" 5.55112e-16 +cap "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/Z3" -1.15019e-13 +cap "mc2" "prescaler_0/tspc_0/a_630_n680#" 328.675 +cap "mc2" "prescaler_0/GND" 319.267 +cap "mc2" "prescaler_0/tspc_0/Z2" 126.915 +cap "prescaler_0/tspc_0/a_630_n680#" "prescaler_0/tspc_0/w_n146_n706#" 5.04167 +cap "prescaler_0/GND" "prescaler_0/tspc_0/w_n146_n706#" 12.1359 +cap "mc2" "prescaler_0/tspc_0/Z2" -393.365 +cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 19.9143 +cap "prescaler_0/nand_0/a_280_n230#" "prescaler_0/nand_0/VDD" 34.0634 +cap "prescaler_0/GND" "prescaler_0/tspc_0/w_n146_n706#" 3.58696 +cap "prescaler_0/nand_0/OUT" "prescaler_0/nand_0/VDD" 5.68434e-14 +cap "prescaler_0/GND" "mc2" 127.942 +cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z2" 1.66533e-15 +cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 4.5 +cap "and_0/Z1" "mc2" 74.215 +cap "gnd" "mc2" 117.19 +cap "and_0/OUT" "mc2" 46.015 +cap "and_0/B" "mc2" 13.94 +cap "and_0/OUT" "vdd" 39.6 +cap "and_0/out1" "mc2" 59.955 +cap "and_0/VDD" "prescaler_0/m1_2700_2190#" 36.6566 +cap "and_0/OUT" "gnd" 22.72 +cap "and_0/VDD" "gnd" 23.0856 +cap "w_n966_n46#" "and_0/Z1" 5.5 +cap "and_0/out1" "and_0/OUT" 48.6223 +cap "w_n966_n46#" "and_0/OUT" 3.20833 +cap "w_n966_n46#" "gnd" 1.50595 +cap "and_0/VDD" "and_0/OUT" 0.870968 +cap "w_n966_n46#" "and_0/out1" 3.20833 +cap "and_0/Z1" "mc2" -164.32 +cap "nor_0/gnd!" "mc2" 364.635 +cap "nor_1/A" "mc2" 12.84 +cap "nor_1/B" "mc2" 12.84 +cap "nor_1/A" "nor_0/gnd!" 1.28205 +cap "nor_1/Out" "mc2" 161.385 +cap "nor_1/Out" "nor_1/Z1" 22.8782 +cap "nor_0/Out" "vdd" 90.78 +cap "nor_0/Out" "nor_1/Z1" 181.56 +cap "and_0/w_n126_n696#" "and_0/Z1" 0.916667 +cap "and_0/w_n126_n696#" "nor_0/gnd!" 2.91667 +cap "nor_1/B" "nor_0/B" 2.64706 +cap "nor_1/Out" "nor_0/gnd!" 16.9459 +cap "nor_1/B" "nor_1/A" 58.3333 +cap "nor_0/Out" "nor_1/A" 15.1125 +cap "nor_0/VDD" "nor_1/A" 0.99 +cap "and_0/w_n126_n696#" "nor_1/Out" 7 +cap "nor_1/Out" "nor_1/B" 13.2 +cap "nor_0/Out" "nor_1/B" 84.4673 +cap "nor_0/Out" "nor_1/Out" 90.78 +cap "nor_0/VDD" "nor_0/Out" 4.29 +cap "nor_0/A" "nor_0/Out" 180.039 +cap "nor_0/A" "nor_0/GND" 305.362 +cap "nor_0/B" "nor_0/Out" 41.7957 +cap "nor_0/VDD" "nor_0/Out" 4.29 +cap "nor_0/B" "nor_0/A" 14.5768 +cap "nor_1/w_n66_n446#" "nor_0/Out" 7 +cap "nor_1/w_n66_n446#" "nor_0/GND" 2 +cap "nor_0/Z1" "nor_1/B" 181.56 +cap "nor_1/B" "vdd" 90.78 +cap "nor_1/B" "nor_0/Out" 90.78 +cap "nor_1/B" "nor_0/A" 15.1125 +cap "nor_1/B" "nor_0/B" 17.7596 +cap "nor_1/B" "nor_0/VDD" -7.41 +cap "prescaler_0/tspc_0/Z2" "prescaler_0/tspc_0/w_n146_n706#" 9.75806 +cap "prescaler_0/tspc_0/a_630_n680#" "prescaler_0/tspc_0/w_n146_n706#" 5.04167 +cap "prescaler_0/GND" "prescaler_0/tspc_0/w_n146_n706#" 12.1359 +cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/GND" 3.58696 +cap "prescaler_0/tspc_0/w_n146_n706#" "prescaler_0/tspc_0/Z2" 4.5 +cap "w_n966_n46#" "and_0/OUT" 3.20833 +cap "and_0/Z1" "w_n966_n46#" 5.5 +cap "and_0/out1" "w_n966_n46#" 3.20833 +cap "gnd" "w_n966_n46#" 9.75595 +cap "nor_0/gnd!" "mc2" 41.6667 +cap "and_0/w_n126_n696#" "and_0/Z1" 0.916667 +cap "and_0/w_n126_n696#" "nor_0/gnd!" 29.5 +cap "and_0/w_n126_n696#" "nor_1/Out" 7 +cap "nor_0/GND" "mc2" 41.6667 +cap "nor_1/w_n66_n446#" "nor_0/Out" 7 +cap "nor_1/w_n66_n446#" "nor_0/GND" 20.3333 +merge "nor_1/gnd!" "nor_0/GND" -277.358 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34184 -2250 0 0 0 0 +merge "nor_0/GND" "nor_1/GND" +merge "nor_1/GND" "nor_0/gnd!" +merge "nor_0/gnd!" "m4_5770_3730#" +merge "m4_5770_3730#" "and_0/GND" +merge "and_0/GND" "m4_4690_3730#" +merge "m4_4690_3730#" "tspc_2/GND" +merge "tspc_2/GND" "tspc_1/gnd!" +merge "tspc_1/gnd!" "tspc_2/gnd!" +merge "tspc_2/gnd!" "tspc_1/GND" +merge "tspc_1/GND" "m4_7020_30#" +merge "m4_7020_30#" "tspc_0/GND" +merge "tspc_0/GND" "prescaler_0/GND" +merge "prescaler_0/GND" "gnd" +merge "prescaler_0/clk" "clk" -41.255 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -600 -200 0 0 0 0 0 0 0 0 +merge "and_0/OUT" "prescaler_0/mc1" -377.58 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -304200 -260 0 0 0 0 0 0 0 0 0 0 0 0 +merge "prescaler_0/mc1" "li_2870_2670#" +merge "prescaler_0/m4_2730_1520#" "tspc_2/vdd!" 648.833 0 0 0 0 677908 -39550 0 0 -119000 -1030 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 219820 -1356 -67080 -1036 -67080 -1036 -67080 -1036 -223132 -7758 0 0 0 0 +merge "tspc_2/vdd!" "tspc_1/vdd!" +merge "tspc_1/vdd!" "m4_7030_1860#" +merge "m4_7030_1860#" "nor_1/vdd!" +merge "nor_1/vdd!" "nor_1/VDD" +merge "nor_1/VDD" "nor_0/vdd!" +merge "nor_0/vdd!" "nor_0/VDD" +merge "nor_0/VDD" "tspc_0/vdd!" +merge "tspc_0/vdd!" "and_0/vdd!" +merge "and_0/vdd!" "vdd" +merge "vdd" "prescaler_0/tspc_1/vdd!" +merge "prescaler_0/tspc_1/vdd!" "and_0/VDD" +merge "and_0/VDD" "prescaler_0/nand_0/vdd!" +merge "prescaler_0/nand_0/vdd!" "li_3310_1810#" +merge "li_3310_1810#" "prescaler_0/nand_0/VDD" +merge "prescaler_0/nand_0/VDD" "tspc_2/w_n140_n70#" +merge "tspc_2/w_n140_n70#" "tspc_1/w_n140_n70#" +merge "tspc_1/w_n140_n70#" "tspc_0/w_n140_n70#" +merge "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/w_n140_n70#" +merge "prescaler_0/tspc_1/w_n140_n70#" "prescaler_0/w_1930_2072#" +merge "prescaler_0/w_1930_2072#" "w_2780_1920#" +merge "nor_0/B" "tspc_2/a_740_n680#" -1145.97 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -144400 -160 163360 -4720 0 0 0 0 0 0 0 0 0 0 +merge "tspc_2/a_740_n680#" "tspc_2/D" +merge "tspc_2/D" "li_7140_680#" +merge "nor_1/B" "tspc_1/a_740_n680#" -563.399 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -48400 -160 -79460 -280 102000 0 0 0 0 0 0 0 0 0 +merge "tspc_1/a_740_n680#" "m1_5770_3360#" +merge "m1_5770_3360#" "tspc_1/D" +merge "tspc_1/D" "li_5560_680#" +merge "nor_1/Out" "and_0/A" -50.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -6800 -160 0 0 0 0 0 0 0 0 0 0 0 0 +merge "and_0/A" "li_4830_3100#" +merge "tspc_2/a_300_n150#" "tspc_1/Q" -145.17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -23400 -160 0 0 -73536 -80 0 0 0 0 0 0 0 0 +merge "tspc_1/Q" "li_7040_820#" +merge "nor_1/A" "tspc_0/a_740_n680#" -251.602 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -39600 -300 6700 -260 70300 0 0 0 0 0 0 0 0 0 +merge "tspc_0/a_740_n680#" "li_5740_3250#" +merge "li_5740_3250#" "tspc_0/D" +merge "tspc_0/D" "li_3980_680#" +merge "nor_1/w_n66_n446#" "nor_0/w_n66_n446#" -12512.4 -245903 -22956 0 0 0 0 0 0 0 0 227114 -18282 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 954823 -49352 0 0 0 0 0 0 0 0 0 0 0 0 +merge "nor_0/w_n66_n446#" "and_0/w_n126_n696#" +merge "and_0/w_n126_n696#" "tspc_2/w_n146_n706#" +merge "tspc_2/w_n146_n706#" "tspc_1/w_n146_n706#" +merge "tspc_1/w_n146_n706#" "tspc_0/w_n146_n706#" +merge "tspc_0/w_n146_n706#" "prescaler_0/VSUBS" +merge "prescaler_0/VSUBS" "w_n966_n46#" +merge "tspc_0/a_300_n150#" "prescaler_0/Out" -31.505 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -6600 -140 0 0 0 0 0 0 0 0 +merge "prescaler_0/Out" "m2_3910_680#" +merge "prescaler_0/tspc_0/vdd!" "prescaler_0/tspc_0/w_n140_n70#" -700.975 0 0 0 0 -223152 -5390 0 0 -41700 -500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -10982 -564 -9340 -564 -13120 -564 -19492 -564 -19184 -820 0 0 0 0 +merge "prescaler_0/tspc_0/w_n140_n70#" "prescaler_0/nand_1/vdd!" +merge "prescaler_0/nand_1/vdd!" "prescaler_0/nand_1/VDD" +merge "prescaler_0/nand_1/VDD" "w_n140_1520#" +merge "nor_0/A" "mc2" 65.105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17200 -80 48400 0 741600 0 0 0 0 0 0 0 0 0 +merge "tspc_1/a_300_n150#" "tspc_0/Q" -124.549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13200 -160 0 0 -47216 -80 0 0 0 0 0 0 0 0 +merge "tspc_0/Q" "li_5460_820#" +merge "nor_0/Out" "and_0/B" -613.41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -293400 -140 6300 -60 0 0 0 0 0 0 0 0 0 0 +merge "and_0/B" "li_6130_3350#" +merge "tspc_2/Q" "Out" -28.98 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1600 -100 0 0 0 0 0 0 0 0 0 0 0 0
diff --git a/gds/filter.ext b/gds/filter.ext new file mode 100644 index 0000000..0b51270 --- /dev/null +++ b/gds/filter.ext
@@ -0,0 +1,31 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__res_xhigh_po l=l w=w +parameters sky130_fd_pr__res_xhigh_po_5p73 l=l +parameters sky130_fd_pr__res_xhigh_po_2p85 l=l +parameters sky130_fd_pr__res_xhigh_po_1p41 l=l +parameters sky130_fd_pr__res_xhigh_po_0p69 l=l +parameters sky130_fd_pr__res_xhigh_po_0p35 l=l +parameters sky130_fd_pr__cap_mim_m3_1 w=w l=l +port "v" 3 4130 -2280 4130 -2280 li +port "gnd!" 2 4310 -20570 4310 -20570 li +port "gnd" 1 4310 -20570 4310 -20570 li +node "a_4294_n4798#" 51429 0 4294 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +node "a_3976_n5230#" 178 415258 3976 -5230 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60480 2008 154056 1592 40000 800 40000 800 177102650 116770 0 0 0 0 +node "a_3976_n4798#" 51429 0 3976 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +node "a_3976_n2998#" 382 1341.76 3976 -2998 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120960 4016 151980 1600 0 0 0 0 0 0 0 0 0 0 +substrate "v" 0 0 4130 -2280 li 6814080 87360 0 0 0 0 0 0 0 0 4732000 72800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51962080 147668 853254 8326 97600 1760 241185900 76920 35214504 24450 0 0 0 0 +equiv "v" "gnd!" +equiv "v" "gnd" +device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -19830 -2459 -19829 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 3600 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -19730 4121 -19729 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 3600 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -13520 -2459 -13519 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 3600 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -13340 4121 -13339 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 3600 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 4770 -7130 4771 -7129 w=6000 l=6000 "None" "v" 23616 0 "v" 3600 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_3976_n5230#" 23616 0 "v" 3600 0 +device rsubckt sky130_fd_pr__res_xhigh_po 4294 -4798 4295 -4797 l=1800 w=70 "v" "a_4294_n4798#" 0 0 "v" 70 0 "a_3976_n2998#" 70 0 +device rsubckt sky130_fd_pr__res_xhigh_po 3976 -4798 3977 -4797 l=1800 w=70 "v" "a_3976_n4798#" 0 0 "a_3976_n5230#" 70 0 "a_3976_n2998#" 70 0
diff --git a/gds/nand.ext b/gds/nand.ext new file mode 100644 index 0000000..6c1b916 --- /dev/null +++ b/gds/nand.ext
@@ -0,0 +1,44 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +port "z1" 5 110 -340 290 -290 li +port "gnd!" 7 12 -502 12 -502 li +port "GND" 4 -40 -620 550 -560 m4 +port "OUT" 1 120 -80 500 -30 li +port "vdd!" 6 260 444 260 444 li +port "A" 2 -50 -210 90 -170 li +port "VDD" 3 -80 520 550 580 nw +node "z1" 1013 195.275 110 -340 li 0 0 0 0 0 0 0 0 32000 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31000 1100 0 0 0 0 0 0 0 0 0 0 0 0 +node "gnd!" 372 610.215 12 -502 li 0 0 0 0 0 0 0 0 16000 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21000 820 5600 300 6400 320 10000 400 39400 1380 0 0 0 0 +equiv "gnd!" "GND" +node "OUT" 3155 852.152 120 -80 li 0 0 0 0 0 0 0 0 16000 560 64000 1920 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 110000 4040 0 0 0 0 0 0 0 0 0 0 0 0 +node "vdd!" 2663 1094 260 444 li 0 0 0 0 0 0 0 0 0 0 64000 1920 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65600 2360 11200 600 12800 640 20000 800 84800 1680 0 0 0 0 +node "a_280_n230#" 1523 573.545 280 -230 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 2060 0 0 9600 480 19000 1160 0 0 0 0 0 0 0 0 0 0 +node "A" 1521 380.56 -50 -210 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32500 2060 0 0 9600 480 0 0 0 0 0 0 0 0 0 0 0 0 +node "VDD" 1727 1248 -80 520 nw 0 0 0 0 416000 2580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "w_n46_n476#" 0 0 -46 -476 pw 123984 1488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "gnd!" "z1" 159.5 +cap "OUT" "z1" 210.754 +cap "OUT" "gnd!" 22 +cap "vdd!" "z1" 8.55556 +cap "a_280_n230#" "z1" 70.125 +cap "vdd!" "gnd!" 8.55556 +cap "A" "z1" 8.25 +cap "vdd!" "OUT" 838.2 +cap "A" "gnd!" 57.75 +cap "a_280_n230#" "OUT" 150.608 +cap "a_280_n230#" "vdd!" 13.0842 +cap "A" "OUT" 9.74286 +cap "A" "vdd!" 13.0842 +cap "VDD" "OUT" 2.96 +cap "VDD" "vdd!" 29.2 +cap "A" "a_280_n230#" 81.6947 +device msubckt sky130_fd_pr__nfet_01v8 310 -450 311 -449 l=30 w=200 "w_n46_n476#" "a_280_n230#" 60 0 "z1" 200 0 "OUT" 200 0 +device msubckt sky130_fd_pr__nfet_01v8 60 -450 61 -449 l=30 w=200 "w_n46_n476#" "A" 60 0 "gnd!" 200 0 "z1" 200 0 +device msubckt sky130_fd_pr__pfet_01v8 310 20 311 21 l=30 w=400 "VDD" "a_280_n230#" 60 0 "vdd!" 400 0 "OUT" 400 0 +device msubckt sky130_fd_pr__pfet_01v8 60 20 61 21 l=30 w=400 "VDD" "A" 60 0 "vdd!" 400 0 "OUT" 400 0
diff --git a/gds/nor.ext b/gds/nor.ext new file mode 100644 index 0000000..2b8fdd3 --- /dev/null +++ b/gds/nor.ext
@@ -0,0 +1,45 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +port "gnd!" 8 236 -468 236 -468 li +port "GND" 1 -110 -580 490 -520 m4 +port "Out" 4 340 -180 490 -140 li +port "Z1" 3 150 400 210 450 li +port "vdd!" 7 -12 934 -12 934 li +port "B" 6 -110 -180 20 -150 m1 +port "A" 5 -110 -80 20 -40 li +port "VDD" 2 -110 990 490 1050 nw +node "gnd!" 1098 1030.73 236 -468 li 0 0 0 0 0 0 0 0 32000 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43000 1680 12800 640 20000 800 20000 800 44000 1480 0 0 0 0 +equiv "gnd!" "GND" +node "Out" 3538 770.477 340 -180 li 0 0 0 0 0 0 0 0 32000 1120 72000 1960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119000 4080 0 0 0 0 0 0 0 0 0 0 0 0 +node "Z1" 5188 577.5 150 400 li 0 0 0 0 0 0 0 0 0 0 144000 3920 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 129000 3900 0 0 0 0 0 0 0 0 0 0 0 0 +node "vdd!" 2400 795.1 -12 934 li 0 0 0 0 0 0 0 0 0 0 72000 1960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68500 2160 6400 320 10000 400 10000 400 40000 1400 0 0 0 0 +node "B" 2203 502.86 -110 -180 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48700 3040 0 0 6400 320 19800 1160 0 0 0 0 0 0 0 0 0 0 +node "A" 2231 379.695 -110 -80 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48700 3040 0 0 9200 460 0 0 0 0 0 0 0 0 0 0 0 0 +node "VDD" 3542 2250 -110 990 nw 0 0 0 0 750000 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "w_n66_n446#" 0 0 -66 -446 pw 123984 1488 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "A" "Out" 8.8 +cap "B" "Z1" 57.75 +cap "VDD" "Out" 2.3125 +cap "A" "vdd!" 57.75 +cap "VDD" "Z1" 2.775 +cap "VDD" "vdd!" 16.2425 +cap "A" "B" 72.9302 +cap "Out" "gnd!" 453.75 +cap "Z1" "gnd!" 9.625 +cap "Z1" "Out" 779.396 +cap "vdd!" "gnd!" 9.625 +cap "B" "gnd!" 39.7045 +cap "vdd!" "Out" 99 +cap "A" "gnd!" 19.25 +cap "vdd!" "Z1" 749.833 +cap "B" "Out" 246.8 +device msubckt sky130_fd_pr__nfet_01v8 290 -420 291 -419 l=30 w=200 "w_n66_n446#" "B" 60 0 "gnd!" 200 0 "Out" 200 0 +device msubckt sky130_fd_pr__nfet_01v8 40 -420 41 -419 l=30 w=200 "w_n66_n446#" "A" 60 0 "gnd!" 200 0 "Out" 200 0 +device msubckt sky130_fd_pr__pfet_01v8 290 20 291 21 l=30 w=900 "VDD" "B" 60 0 "Z1" 900 0 "Out" 900 0 +device msubckt sky130_fd_pr__pfet_01v8 40 20 41 21 l=30 w=900 "VDD" "A" 60 0 "vdd!" 900 0 "Z1" 900 0
diff --git a/gds/pd.ext b/gds/pd.ext new file mode 100644 index 0000000..8a35633 --- /dev/null +++ b/gds/pd.ext
@@ -0,0 +1,158 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +use tspc_r tspc_r_0 1 0 290 0 -1 -850 +use tspc_r tspc_r_1 1 0 290 0 1 760 +use and_pd and_pd_0 1 0 2200 0 1 790 +port "GND" 2 20 -130 2040 40 m4 +port "DIV" 4 -230 -910 -140 -880 m2 +port "REF" 3 -230 790 -140 820 m2 +port "UP" 5 2830 670 2940 700 m1 +port "R" 7 2280 560 2370 590 m2 +port "R" 7 2870 560 2920 610 m2 +port "DOWN" 6 2830 400 2940 430 m1 +port "VDD" 1 -140 -1430 -80 1340 m4 +port "VDD" 1 1960 1260 2040 1280 nw +port "VDD" 1 1960 1200 2100 1260 nw +node "GND" 1 842.66 20 -130 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 343400 4380 0 0 0 0 +node "m4_1440_1280#" 0 173.9 1440 1280 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24600 940 0 0 0 0 +node "DIV" 1 109.532 -230 -910 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6900 520 0 0 0 0 0 0 0 0 +node "REF" 1 109.532 -230 790 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6900 520 0 0 0 0 0 0 0 0 +node "UP" 2 244.23 2830 670 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16200 1140 0 0 0 0 0 0 0 0 0 0 +node "m1_2010_600#" 1 81.02 2010 600 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4800 380 0 0 0 0 0 0 0 0 0 0 +node "R" 26 1557.5 2870 560 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 6400 320 114700 7100 0 0 0 0 0 0 0 0 +node "DOWN" 22 1071.98 2830 400 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 73300 4780 0 0 0 0 0 0 0 0 0 0 +node "VDD" 76 1895.43 -140 -1430 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3200 320 12800 640 16400 720 20000 800 213800 7140 0 0 0 0 +node "w_0_n1460#" 18910 2199.75 0 -1460 nw 0 0 0 0 662500 5900 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 45800 1300 0 0 0 0 +node "VDD" 27087 2548.65 1960 1200 nw 0 0 0 0 793200 7540 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 37400 1040 0 0 0 0 +substrate "w_n446_n1456#" 0 0 -446 -1456 pw 870472 15844 0 0 0 0 0 0 0 0 486400 12160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2463100 27820 0 0 0 0 0 0 0 0 0 0 0 0 +cap "R" "GND" 53.75 +cap "DOWN" "GND" 50.15 +cap "VDD" "GND" 113.9 +cap "m1_2010_600#" "UP" 4.5 +cap "VDD" "DIV" 27.9 +cap "R" "UP" 72 +cap "VDD" "m4_1440_1280#" 4.92 +cap "VDD" "REF" 27.9 +cap "DOWN" "UP" 101.25 +cap "DOWN" "m1_2010_600#" 41.625 +cap "DOWN" "R" 185.417 +cap "VDD" "UP" 7.2 +cap "VDD" "R" 11.2838 +cap "w_0_n1460#" "VDD" 0.48 +cap "VDD" "VDD" 0.48 +cap "tspc_r_0/R" "tspc_r_0/Z3" -7.021 +cap "VDD" "tspc_r_0/Z3" 10.9091 +cap "GND" "tspc_r_0/Z1" 14.4375 +cap "VDD" "DIV" 62.5 +cap "VDD" "tspc_r_0/R" 100 +cap "VDD" "tspc_r_0/Z2" 72 +cap "GND" "tspc_r_0/Z3" 7.21875 +cap "tspc_r_0/w_n290_n40#" "tspc_r_0/Z2" 12.775 +cap "GND" "VDD" 99.8267 +cap "GND" "tspc_r_0/Z2" 9.69375 +cap "tspc_r_0/w_n290_n40#" "VDD" 33.548 +cap "tspc_r_0/Q" "tspc_r_0/VDD" 5.68434e-14 +cap "tspc_r_0/Qbar1" "tspc_r_0/w_n276_n506#" 7.21875 +cap "tspc_r_0/R" "tspc_r_0/Z3" 136.361 +cap "tspc_r_0/Qbar" "tspc_r_0/w_n276_n506#" 7.21875 +cap "tspc_r_0/VDD" "tspc_r_0/w_n276_n506#" 45.2812 +cap "tspc_r_0/Q" "tspc_r_0/w_n276_n506#" 7.21875 +cap "tspc_r_0/VDD" "tspc_r_0/Z3" -2.84217e-14 +cap "tspc_r_0/Qbar" "tspc_r_0/VDD" 30.4615 +cap "tspc_r_1/Z4" "tspc_r_0/Z4" 19.4595 +cap "GND" "tspc_r_0/Z4" 13.3333 +cap "tspc_r_1/Z3" "tspc_r_0/R" -9.042 +cap "GND" "tspc_r_1/Z4" 13.3333 +cap "VDD" "tspc_r_0/R" 66.6667 +cap "GND" "tspc_r_0/R" 64.2857 +cap "VDD" "tspc_r_1/Z2" 72 +cap "VDD" "tspc_r_1/Z3" 10.9091 +cap "VDD" "REF" 44.4444 +cap "GND" "VDD" 148.505 +cap "and_pd_0/Z1" "tspc_r_1/Qbar" 21.0517 +cap "tspc_r_0/Q" "R" 86.5 +cap "tspc_r_1/Q" "R" 150.845 +cap "tspc_r_1/Qbar1" "R" 287.105 +cap "tspc_r_1/Z3" "R" 160.382 +cap "R" "GND" 145.652 +cap "tspc_r_1/clk" "R" 103.99 +cap "tspc_r_1/Q" "and_pd_0/Out1" -12.43 +cap "R" "tspc_r_1/Qbar" 31.025 +cap "tspc_r_1/VDD" "GND" 8.88178e-16 +cap "tspc_r_1/Q" "tspc_r_0/Q" 180.938 +cap "tspc_r_0/Q" "GND" 308.57 +cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 64.7625 +cap "and_pd_0/Out1" "tspc_r_1/Qbar" 45.8071 +cap "tspc_r_0/z5" "GND" 13.3333 +cap "tspc_r_0/Q" "tspc_r_1/Qbar" 17.9186 +cap "tspc_r_0/Q" "and_pd_0/Z1" 76.112 +cap "tspc_r_1/Qbar" "GND" 44.4044 +cap "tspc_r_1/z5" "GND" 13.3333 +cap "tspc_r_0/z5" "tspc_r_1/z5" 19.4595 +cap "R" "tspc_r_0/GND" 16.129 +cap "tspc_r_1/Qbar" "and_pd_0/Z1" 1.76471 +cap "DOWN" "and_pd_0/Z1" -9.852 +cap "and_pd_0/Out1" "R" 137.14 +cap "DOWN" "tspc_r_0/GND" 113.28 +cap "and_pd_0/Out1" "tspc_r_1/Qbar" 1.71875 +cap "UP" "R" 222.129 +cap "DOWN" "R" 90.78 +cap "tspc_r_0/w_n276_n506#" "tspc_r_0/GND" 9.20833 +cap "tspc_r_0/w_n276_n506#" "and_pd_0/Z1" 0.916667 +cap "VDD" "R" 56.5714 +cap "UP" "and_pd_0/Out1" 70.6975 +cap "tspc_r_0/w_n276_n506#" "R" 71.3216 +cap "DOWN" "and_pd_0/Out1" 105.892 +cap "tspc_r_0/w_n276_n506#" "and_pd_0/Out1" 6.41667 +cap "VDD" "UP" 2.66454e-15 +cap "VDD" "and_pd_0/Out1" 12.375 +cap "DOWN" "UP" 61.428 +cap "w_n446_n1456#" "tspc_r_1/Z2" 9.69375 +cap "tspc_r_1/w_n290_n40#" "tspc_r_1/Z2" 12.775 +cap "w_n446_n1456#" "tspc_r_1/Z1" 14.4375 +cap "w_n446_n1456#" "tspc_r_1/Z3" 7.21875 +cap "tspc_r_1/w_n290_n40#" "tspc_r_1/VDD" 33.548 +cap "w_n446_n1456#" "tspc_r_1/VDD" 58.522 +cap "tspc_r_1/Qbar" "and_pd_0/Out1" 5.42143 +cap "and_pd_0/Out1" "w_n446_n1456#" 7.21875 +cap "tspc_r_1/Qbar" "w_n446_n1456#" 7.21875 +cap "w_n446_n1456#" "tspc_r_1/Q" 7.21875 +cap "w_n446_n1456#" "tspc_r_1/Qbar1" 7.21875 +cap "VDD" "tspc_r_1/VDD" 43.262 +cap "tspc_r_1/Q" "and_pd_0/A" 2.15625 +cap "tspc_r_1/Qbar" "tspc_r_1/VDD" 9.4875 +cap "w_n446_n1456#" "tspc_r_1/VDD" 54.6607 +cap "w_n446_n1456#" "and_pd_0/Out" 11.4354 +cap "w_n446_n1456#" "and_pd_0/Out1" 7.21875 +cap "w_n446_n1456#" "VDD" 18.7589 +merge "and_pd_0/w_n86_n496#" "and_pd_0/GND" -6928.56 -101246 -10206 0 0 0 0 0 0 0 0 212812 -7926 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -44382 -19097 0 0 0 0 0 0 -544244 -9300 0 0 0 0 +merge "and_pd_0/GND" "tspc_r_1/w_n276_n506#" +merge "tspc_r_1/w_n276_n506#" "tspc_r_1/GND" +merge "tspc_r_1/GND" "tspc_r_0/GND" +merge "tspc_r_0/GND" "GND" +merge "GND" "tspc_r_0/w_n276_n506#" +merge "tspc_r_0/w_n276_n506#" "w_n446_n1456#" +merge "and_pd_0/A" "tspc_r_0/Q" -456.612 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16392 -160 -23430 -60 0 0 0 0 0 0 0 0 0 0 +merge "tspc_r_0/Q" "DOWN" +merge "and_pd_0/a_n60_n30#" "and_pd_0/VDD" 312.509 0 0 0 0 361220 -10832 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28440 -320 0 0 0 0 0 0 67584 -1940 0 0 0 0 +merge "and_pd_0/VDD" "tspc_r_1/VDD" +merge "tspc_r_1/VDD" "m4_1440_1280#" +merge "m4_1440_1280#" "tspc_r_1/D" +merge "tspc_r_1/D" "tspc_r_1/w_n290_n40#" +merge "tspc_r_1/w_n290_n40#" "tspc_r_0/VDD" +merge "tspc_r_0/VDD" "tspc_r_0/w_n290_n40#" +merge "tspc_r_0/w_n290_n40#" "w_0_n1460#" +merge "w_0_n1460#" "tspc_r_0/D" +merge "tspc_r_0/D" "VDD" +merge "and_pd_0/Out" "tspc_r_1/R" -959.232 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -80 0 0 14724 -460 0 0 0 0 0 0 0 0 +merge "tspc_r_1/R" "tspc_r_0/R" +merge "tspc_r_0/R" "R" +merge "tspc_r_1/clk" "REF" -12.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -60 0 0 0 0 0 0 0 0 +merge "tspc_r_0/clk" "DIV" -12.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -60 0 0 0 0 0 0 0 0 +merge "and_pd_0/B" "UP" -199.048 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -80920 -320 0 0 0 0 0 0 0 0 0 0 +merge "UP" "tspc_r_1/Q" +merge "tspc_r_1/Q" "m1_2010_600#"
diff --git a/gds/prescaler.ext b/gds/prescaler.ext new file mode 100644 index 0000000..a491d54 --- /dev/null +++ b/gds/prescaler.ext
@@ -0,0 +1,211 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +use nand nand_0 -1 0 2650 0 -1 2100 +use nand nand_1 1 0 -110 0 1 540 +use tspc tspc_0 -1 0 1870 0 -1 2450 +use tspc tspc_1 1 0 2210 0 1 590 +use tspc tspc_2 1 0 650 0 1 590 +port "GND" 4 440 -80 450 -20 m4 +port "GND" 4 390 -370 450 -80 m4 +port "VDD" 5 1980 1460 2140 1580 m4 +port "GND" 4 3500 -370 3720 -310 m4 +port "GND" 4 3720 -370 3780 2660 m4 +port "GND" 4 2690 2660 3780 2720 m4 +port "GND" 4 2100 2720 2170 3410 m4 +port "clk" 2 -420 460 510 500 m2 +port "Out" 3 2110 280 3860 310 m2 +port "mc1" 1 2830 1480 2860 2030 m1 +port "mc1" 1 340 1480 2860 1510 m1 +port "mc1" 1 -420 1480 340 1510 m2 +node "m4_1970_n370#" 0 75.68 1970 -370 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8400 400 0 0 0 0 +node "GND" 0 190.26 390 -370 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26300 1000 0 0 0 0 +node "m4_2730_1520#" 1 323.98 2730 1520 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49200 1760 0 0 0 0 +node "VDD" 0 85.656 1980 1460 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20400 580 0 0 0 0 +node "m4_350_1060#" 0 252.457 350 1060 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62400 1480 0 0 0 0 +node "GND" 3 1703 2690 2660 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 265800 8980 0 0 0 0 +node "GND" 1 378.84 2100 2720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 62700 1980 0 0 0 0 +node "clk" 3 379.35 -420 460 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37200 1940 0 0 0 0 0 0 0 0 +node "m2_970_460#" 12 1208.72 970 460 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 106400 6440 0 0 0 0 0 0 0 0 +node "m1_2700_2190#" 12 1187.47 2700 2190 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84000 5660 0 0 0 0 0 0 0 0 0 0 +node "Out" 19 846.75 2110 280 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1600 160 6400 320 60100 3740 0 0 0 0 0 0 0 0 +node "li_3590_420#" 125 2264.03 3590 420 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15000 820 21300 1120 178400 8640 0 0 0 0 0 0 0 0 +node "li_2030_420#" 66 157.38 2030 420 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9600 540 0 0 0 0 0 0 0 0 0 0 0 0 +node "li_450_280#" 76 168.75 450 280 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10000 580 0 0 0 0 0 0 0 0 0 0 0 0 +node "mc1" 150 2026.91 -420 1480 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17600 960 102600 6560 30100 1740 0 0 0 0 0 0 0 0 +node "li_1980_2130#" 199 398.912 1980 2130 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26700 1400 0 0 0 0 0 0 0 0 0 0 0 0 +node "li_n310_330#" 210 1594.32 -310 330 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23700 1320 90500 5720 0 0 0 0 0 0 0 0 0 0 +node "w_390_530#" 14707 435.372 390 530 nw 0 0 0 0 145124 2500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +node "w_1930_2072#" 27928 716.916 1930 2072 nw 0 0 0 0 238972 4204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "GND" "m4_2730_1520#" 23.6471 +cap "mc1" "m4_2730_1520#" 23.175 +cap "m2_970_460#" "VDD" 42 +cap "Out" "GND" 27.9 +cap "mc1" "VDD" 41.675 +cap "li_3590_420#" "clk" 168.462 +cap "mc1" "m4_350_1060#" 84.575 +cap "li_3590_420#" "m2_970_460#" 183.333 +cap "Out" "m1_2700_2190#" 27.465 +cap "li_3590_420#" "m1_2700_2190#" 23.5 +cap "li_2030_420#" "m2_970_460#" 17.38 +cap "li_450_280#" "clk" 28.72 +cap "w_390_530#" "m4_350_1060#" 2.9032 +cap "w_1930_2072#" "VDD" 1.964 +cap "li_3590_420#" "Out" 716.418 +cap "mc1" "m2_970_460#" 37.515 +cap "li_2030_420#" "Out" 197.97 +cap "li_n310_330#" "clk" 28.72 +cap "mc1" "m1_2700_2190#" 63.2343 +cap "li_1980_2130#" "m2_970_460#" 138.025 +cap "w_1930_2072#" "m2_970_460#" 42.9324 +cap "li_n310_330#" "li_3590_420#" 92.2845 +cap "li_n310_330#" "mc1" 37.515 +cap "w_1930_2072#" "mc1" 2.7456 +cap "w_1930_2072#" "li_1980_2130#" 10.7855 +cap "nand_1/OUT" "nand_1/A" 29.5549 +cap "clk" "nand_1/A" 17.42 +cap "nand_1/OUT" "tspc_2/vdd!" 45.9643 +cap "nand_1/OUT" "clk" 127.12 +cap "nand_1/a_280_n230#" "GND" 124.422 +cap "nand_1/a_280_n230#" "tspc_2/Z3" 75.9225 +cap "nand_1/a_280_n230#" "tspc_2/Z2" 56.16 +cap "nand_1/a_280_n230#" "tspc_2/Z4" 106.442 +cap "nand_1/a_280_n230#" "nand_1/z1" 153.26 +cap "nand_1/OUT" "tspc_2/Z4" 12.3811 +cap "nand_1/A" "nand_1/vdd!" 44.8462 +cap "nand_1/OUT" "nand_1/z1" 2.11538 +cap "nand_1/A" "nand_1/a_280_n230#" 13.02 +cap "clk" "nand_1/a_280_n230#" 94.1074 +cap "nand_1/OUT" "nand_1/a_280_n230#" 165.278 +cap "tspc_2/vdd!" "tspc_1/vdd!" 38.2105 +cap "tspc_2/a_740_n680#" "tspc_1/D" 32.1861 +cap "tspc_1/a_300_n150#" "tspc_2/Z3" 198.42 +cap "tspc_2/a_740_n680#" "tspc_1/a_300_n150#" 129.16 +cap "tspc_1/Z4" "li_3590_420#" 51.8 +cap "tspc_1/gnd!" "li_3590_420#" 198.939 +cap "tspc_2/Z4" "li_3590_420#" 107.677 +cap "tspc_1/Z2" "li_3590_420#" 43.32 +cap "tspc_1/D" "li_3590_420#" 142.71 +cap "tspc_1/gnd!" "tspc_2/a_630_n680#" 17.3347 +cap "tspc_2/Z3" "li_3590_420#" 57.62 +cap "tspc_1/a_300_n150#" "li_3590_420#" 83.0378 +cap "tspc_1/Z2" "tspc_1/gnd!" 16.9342 +cap "tspc_1/D" "tspc_1/Z3" 3.50402 +cap "tspc_1/D" "tspc_1/Z4" 102.17 +cap "tspc_2/a_740_n680#" "li_3590_420#" 150.46 +cap "tspc_1/D" "tspc_1/gnd!" 51.0882 +cap "tspc_1/D" "tspc_1/Z2" 85.89 +cap "tspc_1/D" "tspc_1/Z1" 39.5832 +cap "tspc_1/D" "tspc_1/vdd!" 59.1194 +cap "tspc_2/a_740_n680#" "tspc_1/Z4" 4.09091 +cap "tspc_2/a_740_n680#" "tspc_1/Z2" 5.4 +cap "tspc_1/a_300_n150#" "tspc_1/D" 177.533 +cap "tspc_1/Q" "tspc_1/Z4" -74.25 +cap "tspc_1/Q" "GND" 218.86 +cap "tspc_1/Z3" "tspc_1/Q" 156.507 +cap "tspc_1/Z2" "tspc_1/Q" 12.84 +cap "Out" "GND" 39.1 +cap "Out" "tspc_1/Q" 50.6 +cap "Out" "tspc_1/Z4" 76.1789 +cap "tspc_1/a_300_n150#" "tspc_1/Q" 68.7785 +cap "Out" "tspc_1/Z3" 59.529 +cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043 +cap "Out" "tspc_1/Z2" 9.99 +cap "Out" "tspc_1/a_300_n150#" 179.587 +cap "tspc_1/a_740_n680#" "Out" 82.65 +cap "tspc_1/Z4" "tspc_2/a_740_n680#" 1.92857 +cap "nand_1/vdd!" "tspc_2/Z2" 10 +cap "tspc_0/Q" "nand_1/vdd!" 32.5248 +cap "nand_1/VDD" "nand_1/vdd!" -3.656 +cap "nand_1/vdd!" "mc1" 162.542 +cap "tspc_2/Z2" "mc1" 46.8 +cap "nand_1/VDD" "mc1" 9.165 +cap "tspc_2/Q" "tspc_1/Z1" 10.4211 +cap "tspc_2/Z2" "mc1" 17.4522 +cap "VDD" "tspc_2/Q" 44.0676 +cap "tspc_1/Z2" "mc1" 18 +cap "tspc_0/Z2" "mc1" 53.3571 +cap "nand_0/VDD" "mc1" 24.5544 +cap "VDD" "mc1" 414.897 +cap "nand_0/VDD" "tspc_0/a_300_n150#" 2.0976 +cap "tspc_0/a_300_n150#" "VDD" 166.667 +cap "VDD" "tspc_1/Z2" 4.35484 +cap "tspc_0/a_300_n150#" "nand_0/OUT" -6.9 +cap "VDD" "tspc_0/Z2" 10 +cap "nand_0/VDD" "VDD" -11.884 +cap "nand_0/OUT" "nand_0/z1" 6 +cap "nand_0/a_280_n230#" "VDD" 7.33333 +cap "nand_0/OUT" "tspc_0/Z1" 99.6765 +cap "nand_0/VDD" "nand_0/OUT" 8.1659 +cap "nand_0/OUT" "VDD" 272.242 +cap "nand_0/OUT" "nand_0/a_280_n230#" 9.77778 +cap "VDD" "tspc_0/a_300_n150#" 1.66667 +cap "VDD" "tspc_1/Z2" 11.9132 +cap "nand_0/a_280_n230#" "tspc_1/a_740_n680#" 1.36364 +cap "mc1" "tspc_1/Z2" 46.2522 +cap "GND" "VDD" 39.5155 +cap "mc1" "VDD" 227.695 +cap "nand_0/a_280_n230#" "VDD" 13.125 +cap "nand_0/OUT" "nand_0/z1" 2.2 +cap "nand_0/VDD" "VDD" -6.44 +cap "mc1" "nand_0/OUT" 22.3793 +cap "nand_0/a_280_n230#" "nand_0/OUT" 0.275 +cap "nand_0/VDD" "mc1" 9.555 +cap "tspc_0/Q" "tspc_0/a_740_n680#" 18.4737 +cap "nand_0/OUT" "nand_0/z1" 14 +cap "nand_0/OUT" "tspc_0/vdd!" 47.4 +cap "nand_0/OUT" "tspc_0/Z1" 20.5588 +cap "nand_0/OUT" "tspc_0/Z4" 7.71692 +cap "nand_0/OUT" "GND" -5.32907e-15 +cap "tspc_0/a_300_n150#" "nand_0/OUT" 0.18 +cap "tspc_0/Z3" "nand_0/OUT" 5.25747 +cap "tspc_0/w_n140_n70#" "nand_0/OUT" 3.0525 +cap "nand_0/OUT" "nand_0/z1" 3.85 +merge "tspc_0/gnd!" "tspc_0/GND" -422.046 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -213980 -2050 0 0 0 0 +merge "tspc_0/GND" "nand_0/GND" +merge "nand_0/GND" "tspc_1/GND" +merge "tspc_1/GND" "tspc_2/GND" +merge "tspc_2/GND" "tspc_1/gnd!" +merge "tspc_1/gnd!" "m4_1970_n370#" +merge "m4_1970_n370#" "nand_1/GND" +merge "nand_1/GND" "GND" +merge "nand_0/w_n46_n476#" "tspc_0/w_n146_n706#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +merge "tspc_0/w_n146_n706#" "tspc_1/w_n146_n706#" +merge "tspc_1/w_n146_n706#" "tspc_2/w_n146_n706#" +merge "tspc_2/w_n146_n706#" "nand_1/w_n46_n476#" +merge "nand_1/w_n46_n476#" "VSUBS" +merge "nand_0/VDD" "tspc_2/w_n140_n70#" 790.044 0 0 0 0 263348 -15264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +merge "tspc_2/w_n140_n70#" "tspc_0/w_n140_n70#" +merge "tspc_0/w_n140_n70#" "tspc_1/w_n140_n70#" +merge "tspc_1/w_n140_n70#" "w_1930_2072#" +merge "w_1930_2072#" "nand_1/VDD" +merge "nand_1/VDD" "w_390_530#" +merge "tspc_1/vdd!" "tspc_2/vdd!" -1139.18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 -7520 0 0 0 0 +merge "tspc_2/vdd!" "nand_0/vdd!" +merge "nand_0/vdd!" "m4_2730_1520#" +merge "m4_2730_1520#" "VDD" +merge "VDD" "tspc_0/vdd!" +merge "tspc_0/vdd!" "nand_1/vdd!" +merge "nand_1/vdd!" "m4_350_1060#" +merge "tspc_0/a_300_n150#" "tspc_1/a_300_n150#" -475.331 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21000 -500 0 0 0 0 0 0 0 0 +merge "tspc_1/a_300_n150#" "tspc_2/a_300_n150#" +merge "tspc_2/a_300_n150#" "clk" +merge "clk" "m2_970_460#" +merge "nand_0/A" "mc1" -109.389 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -57600 -80 0 0 0 0 0 0 0 0 0 0 0 0 +merge "nand_0/a_280_n230#" "tspc_1/a_740_n680#" 110.67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 244300 -180 0 0 0 0 0 0 0 0 0 0 +merge "tspc_1/a_740_n680#" "m1_2700_2190#" +merge "tspc_1/Q" "nand_1/a_280_n230#" -1317.88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9500 -100 0 -60 -56000 -2800 0 0 0 0 0 0 0 0 +merge "nand_1/a_280_n230#" "li_3590_420#" +merge "tspc_0/D" "nand_0/OUT" -125.318 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -52000 -240 0 0 0 0 0 0 0 0 0 0 0 0 +merge "nand_0/OUT" "li_1980_2130#" +merge "tspc_2/D" "nand_1/OUT" -73.35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2000 -260 0 0 0 0 0 0 0 0 0 0 0 0 +merge "nand_1/OUT" "li_450_280#" +merge "tspc_2/Q" "tspc_1/D" -453.14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33900 -420 0 0 -2400 -190 0 0 0 0 0 0 0 0 +merge "tspc_1/D" "Out" +merge "Out" "li_2030_420#" +merge "tspc_0/Q" "nand_1/A" -90.57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -44400 -180 0 0 0 0 0 0 0 0 0 0 0 0 +merge "nand_1/A" "li_n310_330#"
diff --git a/gds/ro_complete.ext b/gds/ro_complete.ext new file mode 100644 index 0000000..741322c --- /dev/null +++ b/gds/ro_complete.ext
@@ -0,0 +1,174 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +use ro_var_extend ro_var_extend_0 1 0 974 0 1 1350 +use cbank cbank_0 1 0 -84 0 1 -1870 +use cbank cbank_1 1 0 -84 0 1 -8980 +use cbank cbank_2 1 0 -84 0 1 -5410 +port "a5" 3 7346 -1650 7346 -1650 li +port "a4" 4 6144 -1650 6144 -1650 li +port "a3" 5 5182 -1650 5182 -1650 li +port "a2" 6 4202 -1670 4202 -1670 li +port "a1" 2 3234 -1660 3234 -1660 li +port "a0" 1 2246 -1650 2246 -1650 li +node "a5" 1492 5300.76 7346 -1650 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 599200 17260 0 0 0 0 0 0 0 0 0 0 0 0 +node "a4" 1403 4987.24 6144 -1650 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 563500 16240 0 0 0 0 0 0 0 0 0 0 0 0 +node "a3" 1403 4987.24 5182 -1650 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 563500 16240 0 0 0 0 0 0 0 0 0 0 0 0 +node "a2" 1408 5005.68 4202 -1670 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 565600 16300 0 0 0 0 0 0 0 0 0 0 0 0 +node "a1" 1393 4950.35 3234 -1660 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 559300 16120 0 0 0 0 0 0 0 0 0 0 0 0 +node "a0" 1408 5005.68 2246 -1650 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 565600 16300 0 0 0 0 0 0 0 0 0 0 0 0 +node "li_7140_1400#" 85 6989.63 7140 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50400 1320 32400 720 2607360 22208 57600 960 57600 960 0 0 0 0 +node "li_4080_1390#" 94 5201.91 4080 1390 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40000 1240 19600 560 19600 560 1919760 19328 57600 960 0 0 0 0 +node "li_1010_1400#" 88 1456.19 1010 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38800 1200 19600 560 19600 560 19600 560 196600 4100 0 0 0 0 +substrate "w_7764_n10666#" 0 0 7764 -10666 pw 1752192 22464 0 0 0 0 0 0 0 0 1216800 18720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1036800 17280 1349800 21100 1085200 18160 1085200 18160 3951000 27540 0 0 0 0 +cap "li_7140_1400#" "a5" 100.96 +cap "li_4080_1390#" "a5" 77.72 +cap "cbank_1/a0" "cbank_1/switch_5/vout" 46.5385 +cap "cbank_1/a2" "cbank_1/switch_3/vout" 46.5385 +cap "cbank_1/a1" "cbank_1/switch_4/vout" 46.5385 +cap "cbank_1/a3" "cbank_1/switch_2/vout" 46.5385 +cap "cbank_1/a5" "cbank_1/switch_0/vout" 12.6923 +cap "cbank_1/a4" "cbank_1/switch_1/vout" 46.5385 +cap "cbank_1/switch_0/vin" "li_7140_1400#" 23.3333 +cap "cbank_1/a5" "cbank_1/switch_0/vout" 33.8462 +cap "cbank_1/v" "cbank_2/gnd!" 86.7059 +cap "a0" "cbank_1/v" 53.41 +cap "cbank_2/gnd!" "cbank_1/v" 275.882 +cap "cbank_2/switch_4/vin" "a0" 21.2667 +cap "cbank_2/gnd!" "a0" 180.338 +cap "a1" "cbank_1/v" 53.41 +cap "cbank_2/switch_4/vout" "cbank_1/v" 275.882 +cap "cbank_2/switch_4/vout" "a2" 59.4701 +cap "cbank_2/switch_3/vin" "a1" 23.0602 +cap "cbank_2/switch_4/vout" "a1" 208.707 +cap "a3" "cbank_1/v" 53.41 +cap "a2" "cbank_1/v" 53.41 +cap "cbank_2/gnd!" "cbank_1/v" 275.882 +cap "cbank_2/switch_1/vin" "a3" 11.1279 +cap "cbank_2/switch_2/vin" "a2" 22.9222 +cap "cbank_2/gnd!" "a3" 191.198 +cap "cbank_2/gnd!" "a2" 123.77 +cap "a4" "li_7140_1400#" 53.41 +cap "cbank_2/switch_1/vout" "li_7140_1400#" 275.882 +cap "cbank_2/switch_0/vin" "a4" 20.0419 +cap "cbank_2/switch_1/vout" "a4" 189.52 +cap "cbank_2/switch_1/vin" "a3" 11.1279 +cap "cbank_2/switch_0/vout" "w_7764_n10666#" 162.097 +cap "li_7140_1400#" "cbank_1/a_6660_n30#" 126 +cap "cbank_2/switch_0/vout" "li_7140_1400#" 233.936 +cap "cbank_2/switch_0/vout" "a5" 124.366 +cap "cbank_2/gnd!" "w_7764_n10666#" 45.6818 +cap "cbank_2/a0" "cbank_2/switch_4/vin" 107.067 +cap "cbank_2/a0" "cbank_2/switch_5/vout" 249.402 +cap "cbank_2/a2" "cbank_2/switch_3/vout" 150.151 +cap "cbank_2/a1" "cbank_2/switch_3/vin" 116.096 +cap "cbank_2/a1" "cbank_2/switch_4/vout" 290.488 +cap "cbank_2/a3" "cbank_2/switch_1/vin" 56.0233 +cap "cbank_2/a2" "cbank_2/switch_2/vin" 115.401 +cap "cbank_2/a2" "cbank_2/switch_3/vout" 103.613 +cap "cbank_2/gnd!" "cbank_2/a3" 265.538 +cap "cbank_2/switch_1/vin" "a3" 56.0233 +cap "cbank_2/a5" "cbank_2/switch_0/vout" 12.6923 +cap "cbank_2/a4" "cbank_2/switch_0/vin" 100.901 +cap "cbank_2/a4" "cbank_2/switch_1/vout" 263.078 +cap "cbank_2/a5" "cbank_2/switch_0/vout" 143.972 +cap "cbank_0/gnd!" "cbank_2/v" 47.5484 +cap "cbank_0/gnd!" "cbank_2/v" 151.29 +cap "cbank_2/a0" "cbank_2/v" 53.41 +cap "cbank_0/gnd!" "cbank_2/v" 151.29 +cap "cbank_2/a1" "cbank_2/v" 53.41 +cap "cbank_2/a3" "cbank_2/v" 53.41 +cap "cbank_2/a2" "cbank_2/v" 53.41 +cap "cbank_2/w_3654_n56#" "cbank_2/v" 151.29 +cap "cbank_2/a4" "li_4080_1390#" 53.41 +cap "cbank_0/gnd!" "li_4080_1390#" 151.29 +cap "li_4080_1390#" "cbank_0/gnd!" 41.6979 +cap "li_4080_1390#" "cbank_2/switch_0/vin" 133.875 +cap "cbank_2/v" "cbank_0/gnd!" 47.5484 +cap "cbank_0/gnd!" "a0" 294.969 +cap "cbank_0/gnd!" "cbank_2/v" 151.29 +cap "cbank_0/switch_4/vin" "a0" 81.7667 +cap "cbank_2/v" "cbank_0/switch_4/vout" 151.29 +cap "a2" "cbank_0/switch_4/vout" 118.019 +cap "a1" "cbank_0/switch_4/vout" 346.555 +cap "cbank_0/switch_3/vin" "a1" 88.6627 +cap "cbank_0/gnd!" "cbank_2/v" 151.29 +cap "cbank_0/switch_1/vin" "a3" 42.7849 +cap "cbank_0/switch_2/vin" "a2" 88.1317 +cap "cbank_0/gnd!" "a3" 314.948 +cap "cbank_0/gnd!" "a2" 182.319 +cap "li_4080_1390#" "cbank_0/switch_1/vout" 151.29 +cap "cbank_0/switch_0/vin" "a4" 77.0576 +cap "cbank_0/switch_1/vout" "a4" 311.879 +cap "cbank_0/switch_1/vin" "a3" 42.7849 +cap "cbank_0/switch_0/vout" "w_7764_n10666#" 193.269 +cap "cbank_0/switch_0/vout" "a5" 186.594 +cap "cbank_0/switch_0/vout" "li_4080_1390#" 438.698 +cap "cbank_0/switch_0/vout" "li_7140_1400#" 142.26 +cap "cbank_0/gnd!" "w_7764_n10666#" 45.6818 +cap "a0" "cbank_0/switch_5/vout" 134.77 +cap "a0" "cbank_0/switch_4/vin" 46.5667 +cap "a2" "cbank_0/switch_3/vout" 91.603 +cap "a1" "cbank_0/switch_3/vin" 50.494 +cap "a1" "cbank_0/switch_4/vout" 152.64 +cap "a3" "cbank_0/switch_1/vin" 24.3663 +cap "a3" "cbank_0/switch_2/vout" 141.788 +cap "a2" "cbank_0/switch_2/vin" 50.1916 +cap "a2" "cbank_0/switch_3/vout" 45.0645 +cap "cbank_0/switch_0/vout" "cbank_0/a5" 12.6923 +cap "cbank_0/switch_0/vin" "a4" 43.8848 +cap "cbank_0/switch_1/vout" "a4" 140.718 +cap "cbank_0/switch_1/vin" "a3" 24.3663 +cap "a5" "cbank_0/switch_0/vout" 81.7433 +cap "cbank_0/v" "ro_var_extend_0/gnd" 151.9 +cap "li_4080_1390#" "ro_var_extend_0/gnd" 796.97 +cap "ro_var_extend_0/gnd" "li_4080_1390#" 645.27 +cap "ro_var_extend_0/gnd" "li_4080_1390#" 291.625 +cap "ro_var_extend_0/gnd" "li_7140_1400#" 292.345 +cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 69.0462 +cap "ro_var_extend_0/out1" "ro_var_extend_0/w_n120_n750#" 100.15 +cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 129.703 +cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667 +cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023 +cap "ro_var_extend_0/out2" "ro_var_extend_0/w_n120_n750#" 184.5 +cap "ro_var_extend_0/out2" "ro_var_extend_0/gnd" 259.55 +cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031 +cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100 +cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" 322.14 +cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" -11.167 +cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 394.496 +cap "ro_var_extend_0/gnd" "ro_var_extend_0/w_n120_n750#" -86.444 +cap "ro_var_extend_0/gnd" "w_7764_n10666#" -79.966 +merge "cbank_0/a4" "cbank_2/a4" -1880.57 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -239756 -6032 0 0 0 0 0 0 0 0 0 0 0 0 +merge "cbank_2/a4" "cbank_1/a4" +merge "cbank_1/a4" "a4" +merge "ro_var_extend_0/out1" "cbank_0/v" -546.258 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16080 -128 0 0 0 0 0 0 -33984 -1988 0 0 0 0 +merge "cbank_0/v" "li_1010_1400#" +merge "cbank_0/a5" "cbank_2/a5" -1959.7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -328860 -6020 0 0 0 0 0 0 0 0 0 0 0 0 +merge "cbank_2/a5" "cbank_1/a5" +merge "cbank_1/a5" "a5" +merge "ro_var_extend_0/out3" "cbank_1/v" -4738.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14880 -132 0 0 -984344 -18776 -7512 -960 14400 -960 0 0 0 0 +merge "cbank_1/v" "li_7140_1400#" +merge "ro_var_extend_0/out2" "cbank_2/v" -3856.28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -480 -136 0 0 0 0 -669080 -17156 413100 -960 0 0 0 0 +merge "cbank_2/v" "li_4080_1390#" +merge "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/gnd" -1380.79 170112 -2496 0 0 0 0 0 0 0 0 306947 -2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 353653 -1920 265807 -5740 444004 -2800 430320 -2800 231540 -8586 0 0 0 0 +merge "ro_var_extend_0/gnd" "cbank_0/gnd!" +merge "cbank_0/gnd!" "cbank_2/gnd!" +merge "cbank_2/gnd!" "cbank_1/switch_0/vout" +merge "cbank_1/switch_0/vout" "cbank_1/gnd!" +merge "cbank_1/gnd!" "w_7764_n10666#" +merge "cbank_0/a0" "cbank_2/a0" 736.291 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2585720 -6020 0 0 0 0 0 0 0 0 0 0 0 0 +merge "cbank_2/a0" "cbank_1/a0" +merge "cbank_1/a0" "a0" +merge "cbank_0/a1" "cbank_2/a1" -1888.88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -248736 -6032 0 0 0 0 0 0 0 0 0 0 0 0 +merge "cbank_2/a1" "cbank_1/a1" +merge "cbank_1/a1" "a1" +merge "cbank_0/a2" "cbank_2/a2" -1726.65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -69788 -6044 0 0 0 0 0 0 0 0 0 0 0 0 +merge "cbank_2/a2" "cbank_1/a2" +merge "cbank_1/a2" "a2" +merge "cbank_0/a3" "cbank_2/a3" -331.029 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1438996 -6044 0 0 0 0 0 0 0 0 0 0 0 0 +merge "cbank_2/a3" "cbank_1/a3" +merge "cbank_1/a3" "a3"
diff --git a/gds/ro_var_extend.ext b/gds/ro_var_extend.ext new file mode 100644 index 0000000..bed1989 --- /dev/null +++ b/gds/ro_var_extend.ext
@@ -0,0 +1,42 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +parameters sky130_fd_pr__cap_var_lvt l=l w=w a1=as a2=ad p1=ps p2=pd +port "vcont" 5 6286 -610 6286 -610 li +port "out2" 2 3074 190 3074 190 li +port "out1" 1 10 200 10 200 li +port "out3" 4 6130 190 6130 190 li +port "out3" 4 6220 260 6220 260 m1 +port "vdd" 6 6020 900 6020 900 li +port "gnd" 3 5980 -160 5980 -160 li +node "vcont" 61 123.78 6286 -610 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5780 408 0 0 0 0 0 0 0 0 0 0 0 0 +node "out2" 2945 4489.03 3074 190 li 0 0 0 0 0 0 0 0 20000 600 40000 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70084 2720 0 0 240124 7740 240088 7712 0 0 0 0 0 0 0 0 0 0 +node "out1" 2948 5653.45 10 200 li 0 0 0 0 0 0 0 0 20000 600 40000 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70084 2720 0 0 240084 7768 367400 7548 0 0 0 0 0 0 0 0 0 0 +node "out3" 2411 3990.47 6220 260 m1 0 0 0 0 0 0 0 0 20000 600 40000 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70084 2720 0 0 76164 2368 111640 2644 647000 13140 0 0 0 0 0 0 0 0 +node "w_n120_n750#" 20671 4346.02 -120 -750 nw 0 0 0 0 363304 4204 0 0 116400 3564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37536 2616 1153264 13180 0 0 0 0 0 0 0 0 0 0 +node "vdd" 21463 18367.8 6020 900 li 0 0 0 0 4464300 14320 0 0 105600 2580 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "gnd" 0 0 5980 -160 li 2627212 34004 0 0 0 0 0 0 60000 1800 1604600 26100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7902720 57188 0 0 0 0 0 0 0 0 0 0 0 0 +cap "vcont" "w_n120_n750#" 140.194 +cap "out2" "w_n120_n750#" 789.263 +cap "out1" "w_n120_n750#" 569.035 +cap "out2" "vdd" 235.622 +cap "out3" "w_n120_n750#" 215.464 +cap "out1" "vdd" 230.66 +cap "out3" "vdd" 230.554 +cap "out1" "out2" 40.8506 +cap "out3" "out2" 1263.05 +cap "out3" "out1" 1156.32 +device subckt sky130_fd_pr__cap_var_lvt 5955 -694 5956 -693 l=36 w=200 "w_n120_n750#" "out3" 72 0 "w_n120_n750#" 400 0 +device subckt sky130_fd_pr__cap_var_lvt 2991 -690 2992 -689 l=36 w=200 "w_n120_n750#" "out2" 72 0 "w_n120_n750#" 400 0 +device subckt sky130_fd_pr__cap_var_lvt 17 -688 18 -687 l=36 w=200 "w_n120_n750#" "out1" 72 0 "w_n120_n750#" 400 0 +device msubckt sky130_fd_pr__nfet_01v8 6020 -20 6021 -19 l=60 w=200 "gnd" "out2" 120 0 "gnd" 200 0 "out3" 200 0 +device msubckt sky130_fd_pr__nfet_01v8 2964 -20 2965 -19 l=60 w=200 "gnd" "out1" 120 0 "gnd" 200 0 "out2" 200 0 +device msubckt sky130_fd_pr__nfet_01v8 -110 -20 -109 -19 l=60 w=200 "gnd" "out3" 120 0 "gnd" 200 0 "out1" 200 0 +device msubckt sky130_fd_pr__pfet_01v8 6020 360 6021 361 l=60 w=400 "vdd" "out2" 120 0 "vdd" 400 0 "out3" 400 0 +device msubckt sky130_fd_pr__pfet_01v8 2964 360 2965 361 l=60 w=400 "vdd" "out1" 120 0 "vdd" 400 0 "out2" 400 0 +device msubckt sky130_fd_pr__pfet_01v8 -110 360 -109 361 l=60 w=400 "vdd" "out3" 120 0 "vdd" 400 0 "out1" 400 0
diff --git a/gds/switch.ext b/gds/switch.ext new file mode 100644 index 0000000..b9c796c --- /dev/null +++ b/gds/switch.ext
@@ -0,0 +1,18 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +port "vout" 3 210 1410 210 1410 li +port "vin" 2 -150 1410 -150 1410 li +port "vcont" 1 20 1590 20 1590 li +node "vout" 1082 0 210 1410 li 0 0 0 0 0 0 0 0 259200 3240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196000 3080 0 0 0 0 0 0 0 0 0 0 0 0 +node "vin" 1082 0 -150 1410 li 0 0 0 0 0 0 0 0 259200 3240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196000 3080 0 0 0 0 0 0 0 0 0 0 0 0 +node "vcont" 1139 384.82 20 1590 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124600 3560 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "w_n216_n26#" 0 0 -216 -26 pw 719144 3948 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "vin" "vout" 420 +cap "vcont" "vout" 16.5 +cap "vcont" "vin" 8.25 +device msubckt sky130_fd_pr__nfet_01v8 -10 0 -9 1 l=70 w=1440 "w_n216_n26#" "vcont" 140 0 "vin" 1440 0 "vout" 1440 0
diff --git a/gds/tspc.ext b/gds/tspc.ext new file mode 100644 index 0000000..6d3ad8a --- /dev/null +++ b/gds/tspc.ext
@@ -0,0 +1,93 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +port "gnd!" 9 404 -758 404 -758 li +port "GND" 7 -110 -940 1320 -910 m4 +port "Z4" 4 150 -440 660 -410 m1 +port "Q" 5 1260 -170 1380 -120 li +port "Z3" 3 630 -130 1020 -90 li +port "Z3" 3 980 -410 1020 -90 li +port "Z3" 3 260 -220 670 -190 m1 +port "Z2" 6 10 -780 270 -740 li +port "Z1" 2 130 180 220 230 li +port "D" 1 -20 -130 80 -90 li +port "D" 1 -20 -510 20 -90 li +port "vdd!" 8 538 672 538 672 li +node "a_630_n680#" 1081 523.53 630 -680 ndif 0 0 0 0 0 0 0 0 32000 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38200 1520 21000 1160 0 0 0 0 0 0 0 0 0 0 +node "gnd!" 2907 2360.79 404 -758 li 0 0 0 0 0 0 0 0 84000 2740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 114900 4300 25600 1280 25600 1280 40000 1600 153400 3840 0 0 0 0 +equiv "gnd!" "GND" +node "Z4" 1570 408.187 150 -440 m1 0 0 0 0 0 0 0 0 57600 1760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58700 2100 33400 1820 0 0 0 0 0 0 0 0 0 0 +node "Q" 2876 612.45 1260 -170 li 0 0 0 0 0 0 0 0 32000 960 64000 1760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105400 3380 0 0 0 0 0 0 0 0 0 0 0 0 +node "Z3" 3758 1322.86 260 -220 m1 0 0 0 0 0 0 0 0 28800 880 46400 1320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33200 2000 0 0 108400 4040 24200 1240 0 0 0 0 0 0 0 0 0 0 +node "Z2" 2567 891.35 10 -780 li 0 0 0 0 0 0 0 0 7200 340 44800 1280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 1200 0 0 67900 2520 60500 3760 0 0 0 0 0 0 0 0 0 0 +node "Z1" 3420 407 130 180 li 0 0 0 0 0 0 0 0 0 0 89600 2560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82900 2600 0 0 0 0 0 0 0 0 0 0 0 0 +node "a_300_n150#" 4405 1377.57 300 -150 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 89700 5660 0 0 37800 1660 6400 320 27200 1260 0 0 0 0 0 0 0 0 +node "D" 1793 737.785 -20 -510 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38000 2320 0 0 32000 1480 0 0 0 0 0 0 0 0 0 0 0 0 +node "vdd!" 7516 2851.75 538 672 li 0 0 0 0 0 0 0 0 0 0 179200 5120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203700 6980 22400 1200 32000 1440 43200 1680 147600 4620 0 0 0 0 +node "a_740_n680#" 3851 1353.54 740 -680 ndif 0 0 0 0 0 0 0 0 16000 560 24000 760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3440 0 0 51300 2040 67500 3960 0 0 0 0 0 0 0 0 0 0 +node "w_n140_n70#" 2516 4440 -140 -70 nw 0 0 0 0 1480000 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "w_n146_n706#" 0 0 -146 -706 pw 475604 4208 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "gnd!" "a_630_n680#" 610.469 +cap "Z4" "a_630_n680#" 121.707 +cap "Q" "a_630_n680#" 36.6667 +cap "Z4" "gnd!" 441.644 +cap "Z3" "a_630_n680#" 54.2903 +cap "Q" "gnd!" 289.808 +cap "Z2" "a_630_n680#" 6.6 +cap "Z3" "gnd!" 265.176 +cap "Z3" "Z4" 651.52 +cap "Z2" "gnd!" 156.712 +cap "Z2" "Z4" 361.112 +cap "a_300_n150#" "a_630_n680#" 9.625 +cap "Z3" "Q" 52.8649 +cap "a_300_n150#" "gnd!" 22.7597 +cap "Z1" "Z4" 3.38462 +cap "D" "gnd!" 27.9314 +cap "a_300_n150#" "Z4" 118.945 +cap "Z2" "Z3" 161.5 +cap "a_740_n680#" "a_630_n680#" 190.867 +cap "D" "Z4" 97.7372 +cap "Z1" "Z3" 62.0085 +cap "a_740_n680#" "gnd!" 224.895 +cap "vdd!" "Z4" 7.7 +cap "Z1" "Z2" 1068.12 +cap "a_300_n150#" "Z3" 446.312 +cap "a_740_n680#" "Z4" 82.0167 +cap "D" "Z3" 46.1286 +cap "vdd!" "Q" 607.82 +cap "a_300_n150#" "Z2" 110.226 +cap "a_740_n680#" "Q" 178.823 +cap "vdd!" "Z3" 671.367 +cap "D" "Z2" 91.0218 +cap "D" "Z1" 26.4 +cap "vdd!" "Z2" 359.159 +cap "w_n140_n70#" "Q" 6.845 +cap "a_740_n680#" "Z3" 334.495 +cap "vdd!" "Z1" 583.229 +cap "w_n140_n70#" "Z3" 2.3125 +cap "D" "a_300_n150#" 132.679 +cap "vdd!" "a_300_n150#" 20.3736 +cap "w_n140_n70#" "Z2" 14.44 +cap "a_740_n680#" "a_300_n150#" 12.4103 +cap "vdd!" "D" 19.4229 +cap "w_n140_n70#" "Z1" 4.1625 +cap "w_n140_n70#" "a_300_n150#" 0.665 +cap "a_740_n680#" "vdd!" 515.003 +cap "w_n140_n70#" "vdd!" 85.4425 +cap "w_n140_n70#" "a_740_n680#" 18.5775 +device msubckt sky130_fd_pr__nfet_01v8 1210 -680 1211 -679 l=30 w=400 "w_n146_n706#" "a_740_n680#" 60 0 "gnd!" 400 0 "Q" 400 0 +device msubckt sky130_fd_pr__nfet_01v8 960 -680 961 -679 l=30 w=200 "w_n146_n706#" "Z3" 60 0 "gnd!" 200 0 "a_630_n680#" 200 0 +device msubckt sky130_fd_pr__nfet_01v8 710 -680 711 -679 l=30 w=200 "w_n146_n706#" "a_300_n150#" 60 0 "a_630_n680#" 200 0 "a_740_n680#" 200 0 +device msubckt sky130_fd_pr__nfet_01v8 460 -680 461 -679 l=30 w=360 "w_n146_n706#" "a_300_n150#" 60 0 "gnd!" 360 0 "Z4" 360 0 +device msubckt sky130_fd_pr__nfet_01v8 210 -680 211 -679 l=30 w=360 "w_n146_n706#" "Z2" 60 0 "Z4" 360 0 "Z3" 360 0 +device msubckt sky130_fd_pr__nfet_01v8 -40 -680 -39 -679 l=30 w=90 "w_n146_n706#" "D" 60 0 "gnd!" 90 0 "Z2" 90 0 +device msubckt sky130_fd_pr__pfet_01v8 1130 -20 1131 -19 l=30 w=800 "w_n140_n70#" "a_740_n680#" 60 0 "vdd!" 800 0 "Q" 800 0 +device msubckt sky130_fd_pr__pfet_01v8 860 -20 861 -19 l=30 w=300 "w_n140_n70#" "Z3" 60 0 "vdd!" 300 0 "a_740_n680#" 300 0 +device msubckt sky130_fd_pr__pfet_01v8 580 -20 581 -19 l=30 w=580 "w_n140_n70#" "a_300_n150#" 60 0 "vdd!" 580 0 "Z3" 580 0 +device msubckt sky130_fd_pr__pfet_01v8 300 -20 301 -19 l=30 w=560 "w_n140_n70#" "a_300_n150#" 60 0 "Z1" 560 0 "Z2" 560 0 +device msubckt sky130_fd_pr__pfet_01v8 20 -20 21 -19 l=30 w=560 "w_n140_n70#" "D" 60 0 "vdd!" 560 0 "Z1" 560 0
diff --git a/gds/tspc_r.ext b/gds/tspc_r.ext new file mode 100644 index 0000000..04a3ff2 --- /dev/null +++ b/gds/tspc_r.ext
@@ -0,0 +1,112 @@ +timestamp 0 +version 8.3 +tech sky130A +style ngspice() +scale 1000 1 500000 +resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd +port "z5" 4 770 -600 1170 -570 m1 +port "Z4" 11 10 -600 420 -570 m1 +port "GND" 13 -240 -720 1750 -660 m4 +port "R" 8 -290 -230 -180 -200 m2 +port "Qbar" 2 1630 -300 1680 -210 li +port "Z2" 9 -120 -170 -90 0 m1 +port "Z2" 9 -120 -300 -80 -230 li +port "Z1" 10 -60 110 100 160 li +port "VDD" 1 -250 520 1750 580 m4 +port "Q" 3 1520 -160 1750 -130 m1 +port "Qbar1" 5 1120 -230 1200 -200 m1 +port "Qbar1" 5 910 -230 990 -200 m1 +port "Z3" 12 870 -90 950 -50 li +port "Z3" 12 1060 -250 1100 -50 li +port "Z3" 12 650 -300 690 -170 li +port "clk" 6 220 -100 500 -60 li +port "clk" 6 -290 30 -260 60 m2 +port "clk" 6 520 -100 650 -70 m1 +port "clk" 6 810 -170 840 -90 m1 +port "D" 7 -290 -120 -170 -80 li +node "z5" 1038 523.365 770 -600 m1 0 0 0 0 0 0 0 0 28800 1040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34800 1480 21200 1140 0 0 0 0 0 0 0 0 0 0 +node "Z4" 1038 527.66 10 -600 m1 0 0 0 0 0 0 0 0 28800 1040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34800 1480 21500 1160 0 0 0 0 0 0 0 0 0 0 +node "GND" 3842 3467.95 -240 -720 m4 0 0 0 0 0 0 0 0 86400 3120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 145800 5880 38400 1920 60000 2400 60000 2400 164400 4880 0 0 0 0 +node "R" 553 487.18 -290 -230 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15300 900 0 0 6400 320 6400 320 34300 2020 0 0 0 0 0 0 0 0 +node "Qbar" 1331 375.025 1630 -300 li 0 0 0 0 0 0 0 0 14400 520 28800 880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 52800 1860 0 0 0 0 0 0 0 0 0 0 0 0 +node "Z2" 1951 836.922 -120 -300 li 0 0 0 0 0 0 0 0 14400 520 28800 880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15100 900 0 0 58900 2280 41000 2460 0 0 0 0 0 0 0 0 0 0 +node "Z1" 2408 335.5 -60 110 li 0 0 0 0 0 0 0 0 0 0 57600 1760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58400 1940 0 0 0 0 0 0 0 0 0 0 0 0 +node "VDD" 6947 3209.71 -250 520 m4 0 0 0 0 0 0 0 0 0 0 144000 4400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 168000 6400 32000 1600 50000 2000 50000 2000 157800 4780 0 0 0 0 +node "Q" 2845 933.88 1520 -160 m1 0 0 0 0 0 0 0 0 14400 520 28800 880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34600 2100 0 0 66000 2440 11500 660 0 0 0 0 0 0 0 0 0 0 +node "Qbar1" 2917 855.69 910 -230 m1 0 0 0 0 0 0 0 0 14400 520 28800 880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34600 2200 0 0 44200 1680 35400 1920 0 0 0 0 0 0 0 0 0 0 +node "Z3" 3667 1259.1 650 -300 li 0 0 0 0 0 0 0 0 28800 1040 28800 880 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34700 2100 0 0 98000 4000 35900 2120 0 0 0 0 0 0 0 0 0 0 +node "clk" 3201 1422.11 810 -170 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69400 4200 0 0 39600 1820 29100 1560 31300 1820 0 0 0 0 0 0 0 0 +node "D" 1470 418.74 -290 -120 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34600 2100 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0 +node "w_n290_n40#" 7882 2692.8 -290 -40 nw 0 0 0 0 897600 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +substrate "w_n276_n506#" 0 0 -276 -506 pw 462144 4448 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "Z4" "z5" 42.0885 +cap "GND" "z5" 558.112 +cap "GND" "Z4" 527.304 +cap "R" "GND" 35.3744 +cap "Qbar" "GND" 138.6 +cap "Z2" "Z4" 137.657 +cap "VDD" "z5" 6.6 +cap "Z2" "GND" 142.361 +cap "Q" "z5" 33 +cap "Z2" "R" 208.97 +cap "Qbar1" "z5" 203.056 +cap "VDD" "GND" 17.6 +cap "Z3" "z5" 110 +cap "Q" "GND" 263.95 +cap "Z3" "Z4" 201.943 +cap "Qbar1" "GND" 157.761 +cap "clk" "z5" 38.3774 +cap "VDD" "Qbar" 237.6 +cap "Z1" "Z2" 709.991 +cap "Qbar1" "R" 11.3571 +cap "Z3" "GND" 324.951 +cap "clk" "Z4" 18.15 +cap "Q" "Qbar" 213.204 +cap "VDD" "Z2" 95.0921 +cap "Qbar1" "Qbar" 7.54286 +cap "clk" "GND" 37.5833 +cap "Z3" "R" 137.379 +cap "VDD" "Z1" 316.564 +cap "D" "GND" 14.4375 +cap "clk" "R" 508.778 +cap "Q" "VDD" 334.95 +cap "Z3" "Z2" 249.04 +cap "D" "R" 16.14 +cap "Qbar1" "VDD" 315.732 +cap "Z3" "Z1" 85.3 +cap "clk" "Z2" 187.91 +cap "Z3" "VDD" 509.325 +cap "clk" "Z1" 170.927 +cap "w_n290_n40#" "Qbar" 1.85 +cap "D" "Z2" 47.3222 +cap "Qbar1" "Q" 109.835 +cap "clk" "VDD" 129.37 +cap "w_n290_n40#" "Z2" 3.04 +cap "Z3" "Q" 28.6775 +cap "D" "VDD" 38.5 +cap "w_n290_n40#" "Z1" 7.4 +cap "Z3" "Qbar1" 379.384 +cap "w_n290_n40#" "VDD" 7.4 +cap "clk" "Qbar1" 121.715 +cap "w_n290_n40#" "Q" 1.85 +cap "clk" "Z3" 652.716 +cap "w_n290_n40#" "Qbar1" 1.82 +cap "w_n290_n40#" "Z3" 11.56 +cap "D" "clk" 31.5485 +cap "w_n290_n40#" "clk" 10.355 +device msubckt sky130_fd_pr__nfet_01v8 1580 -480 1581 -479 l=30 w=180 "w_n276_n506#" "Q" 60 0 "GND" 180 0 "Qbar" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 1330 -480 1331 -479 l=30 w=180 "w_n276_n506#" "Qbar1" 60 0 "GND" 180 0 "Q" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 1080 -480 1081 -479 l=30 w=180 "w_n276_n506#" "Z3" 60 0 "GND" 180 0 "z5" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 830 -480 831 -479 l=30 w=180 "w_n276_n506#" "clk" 60 0 "z5" 180 0 "Qbar1" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 580 -480 581 -479 l=30 w=180 "w_n276_n506#" "R" 60 0 "GND" 180 0 "Z3" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 330 -480 331 -479 l=30 w=180 "w_n276_n506#" "clk" 60 0 "GND" 180 0 "Z4" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 80 -480 81 -479 l=30 w=180 "w_n276_n506#" "Z2" 60 0 "Z4" 180 0 "Z3" 180 0 +device msubckt sky130_fd_pr__nfet_01v8 -170 -480 -169 -479 l=30 w=180 "w_n276_n506#" "D" 60 0 "GND" 180 0 "Z2" 180 0 +device msubckt sky130_fd_pr__pfet_01v8 1580 0 1581 1 l=30 w=360 "w_n290_n40#" "Q" 60 0 "VDD" 360 0 "Qbar" 360 0 +device msubckt sky130_fd_pr__pfet_01v8 1230 0 1231 1 l=30 w=360 "w_n290_n40#" "Qbar1" 60 0 "VDD" 360 0 "Q" 360 0 +device msubckt sky130_fd_pr__pfet_01v8 880 0 881 1 l=30 w=360 "w_n290_n40#" "Z3" 60 0 "VDD" 360 0 "Qbar1" 360 0 +device msubckt sky130_fd_pr__pfet_01v8 530 0 531 1 l=30 w=360 "w_n290_n40#" "clk" 60 0 "VDD" 360 0 "Z3" 360 0 +device msubckt sky130_fd_pr__pfet_01v8 180 0 181 1 l=30 w=360 "w_n290_n40#" "clk" 60 0 "Z1" 360 0 "Z2" 360 0 +device msubckt sky130_fd_pr__pfet_01v8 -170 0 -169 1 l=30 w=360 "w_n290_n40#" "D" 60 0 "VDD" 360 0 "Z1" 360 0
diff --git a/gds/user_analog_project_wrapper.ext b/gds/user_analog_project_wrapper.ext index 9b0a0c8..82a1a5e 100644 --- a/gds/user_analog_project_wrapper.ext +++ b/gds/user_analog_project_wrapper.ext
@@ -4,7 +4,12 @@ style ngspice() scale 1000 1 500000 resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 -use cp cp_0 1 0 531400 0 1 683270 +use ro_complete ro_complete_0 1 0 31596 0 1 681444 +use pd pd_0 1 0 87306 0 1 647408 +use divider divider_0 1 0 163690 0 1 648664 +use filter filter_0 1 0 224356 0 1 680484 +use cp cp_0 1 0 196464 0 1 608714 +use cp cp_1 1 0 531400 0 1 683270 port "io_analog[4]" 42 329294 702300 334294 704800 m5 port "io_analog[4]" 42 318994 702300 323994 704800 m5 port "io_analog[5]" 43 227594 702300 232594 704800 m5 @@ -1388,60 +1393,65 @@ node "w_534690_682780#" 2061 2427.03 534690 682780 nw 0 0 0 0 171600 1660 0 0 78300 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67500 1040 67500 1040 67500 1040 171600 1660 1425600 9300 0 0 0 0 node "w_534750_683750#" 17515 3366 534750 683750 nw 0 0 0 0 1122000 7460 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "io_analog[4]" "io_analog[4]" 26250 +cap "io_analog[5]" "io_analog[5]" 26250 cap "io_analog[5]" "io_analog[5]" 26250 cap "io_analog[4]" "io_analog[4]" 21250 -cap "io_analog[1]" "io_analog[0]" 12301.4 cap "io_analog[6]" "io_analog[6]" 26250 cap "io_analog[4]" "io_analog[4]" 21250 +cap "io_analog[1]" "io_analog[0]" 12301.4 cap "io_analog[5]" "io_analog[5]" 21250 -cap "w_534750_683750#" "w_534690_682780#" 224.4 cap "io_analog[6]" "io_analog[6]" 26250 -cap "io_analog[0]" "vdda1" 18313.2 -cap "io_analog[1]" "vdda1" 23516.2 cap "io_analog[5]" "io_analog[5]" 21250 -cap "io_analog[2]" "vdda1" 219.25 cap "io_analog[6]" "io_analog[6]" 21250 -cap "io_analog[3]" "vssa1" 6389.64 -cap "io_analog[2]" "vssa1" 9275.17 cap "io_analog[6]" "io_analog[6]" 21250 +cap "w_534750_683750#" "w_534690_682780#" 224.4 cap "io_clamp_high[0]" "io_analog[4]" 525 cap "io_clamp_low[0]" "io_clamp_high[0]" 525 cap "io_analog[4]" "io_clamp_low[0]" 525 cap "io_clamp_high[1]" "io_analog[5]" 525 cap "io_clamp_low[1]" "io_clamp_high[1]" 525 +cap "io_analog[0]" "vdda1" 18313.2 cap "io_analog[5]" "io_clamp_low[1]" 525 +cap "io_analog[1]" "vdda1" 23516.2 +cap "io_analog[2]" "vdda1" 219.25 +cap "io_analog[3]" "vssa1" 6389.64 cap "io_clamp_high[2]" "io_analog[6]" 525 +cap "io_analog[2]" "vssa1" 9275.17 cap "io_analog[4]" "io_analog[4]" 26250 cap "io_clamp_low[2]" "io_clamp_high[2]" 525 cap "io_analog[6]" "io_clamp_low[2]" 525 -cap "io_analog[4]" "io_analog[4]" 26250 -cap "io_analog[5]" "io_analog[5]" 26250 -cap "cp_0/w_6344_n2866#" "cp_0/down" 439.89 -cap "cp_0/gnd!" "io_analog[1]" -20.89 -cap "cp_0/vbias" "cp_0/gnd!" 6.79412 -cap "cp_0/vbias" "cp_0/gnd!" 8.73529 -cap "cp_0/vbias" "cp_0/gnd!" 6.79412 -cap "cp_0/vbias" "cp_0/gnd!" 8.73529 -cap "cp_0/a_10_n50#" "cp_0/vbias" 31.68 -cap "w_534750_683750#" "cp_0/a_1710_0#" 37.5 -cap "w_534750_683750#" "cp_0/a_3060_0#" 99.11 -cap "w_534750_683750#" "cp_0/a_3060_0#" 243.801 -cap "cp_0/a_3060_0#" "w_534690_682780#" 1083.86 +cap "cp_1/w_6344_n2866#" "cp_1/down" 439.89 +cap "cp_1/gnd!" "io_analog[1]" -20.89 +cap "cp_1/vbias" "cp_1/gnd!" 6.79412 +cap "cp_1/vbias" "cp_1/gnd!" 8.73529 +cap "cp_1/vbias" "cp_1/gnd!" 6.79412 +cap "cp_1/a_10_n50#" "cp_1/vbias" 31.68 +cap "cp_1/gnd!" "cp_1/vbias" 8.73529 +cap "cp_1/a_3060_0#" "w_534750_683750#" 99.11 +cap "w_534750_683750#" "cp_1/a_3060_0#" 243.801 +cap "cp_1/a_1710_0#" "w_534750_683750#" 37.5 +cap "cp_1/a_3060_0#" "w_534690_682780#" 1083.86 cap "w_534750_683750#" "w_534690_682780#" -39.04 -cap "cp_0/a_3060_0#" "w_534690_682780#" 904.4 +cap "cp_1/a_3060_0#" "w_534690_682780#" 904.4 cap "w_534750_683750#" "w_534690_682780#" -28 -cap "cp_0/a_3060_0#" "w_534690_682780#" 50.49 -cap "cp_0/a_3060_0#" "w_534690_682780#" 119.25 -cap "w_534750_683750#" "w_534690_682780#" -15.96 -cap "cp_0/vdd!" "cp_0/vdd!" 27.826 -cap "cp_0/vdd!" "cp_0/upbar" 248.023 -merge "cp_0/a_1710_n2840#" "vdda1" -22610.2 0 0 0 0 -6894710 -17723 0 0 81500 -1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158488 -1040 161588 -1040 172532 -1040 1278340 -5232 484262 -11742 0 0 0 0 -merge "vdda1" "cp_0/vdd!" -merge "cp_0/vdd!" "w_534690_682780#" +cap "cp_1/a_3060_0#" "w_534690_682780#" 119.25 +cap "w_534690_682780#" "w_534750_683750#" -15.96 +cap "cp_1/a_3060_0#" "w_534690_682780#" 50.49 +cap "cp_1/vdd!" "cp_1/vdd!" 27.826 +cap "cp_1/vdd!" "cp_1/upbar" 248.023 +merge "cp_1/a_1710_n2840#" "vdda1" -22610.2 0 0 0 0 -6894710 -17723 0 0 81500 -1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158488 -1040 161588 -1040 172532 -1040 1278340 -5232 484262 -11742 0 0 0 0 +merge "vdda1" "cp_1/vdd!" +merge "cp_1/vdd!" "w_534690_682780#" merge "w_534690_682780#" "w_534750_683750#" -merge "cp_0/gnd!" "VSUBS" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0 -merge "VSUBS" "vssa1" -merge "cp_0/out" "io_analog[0]" -3017.14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148470 -1462 0 0 -4960000 -6468 0 0 0 0 0 0 -merge "cp_0/down" "io_analog[1]" -8136.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -173112 -2410 8212 -870 -227646 -1840 -12500000 -15000 0 0 0 0 0 0 -merge "cp_0/vbias" "io_analog[3]" -6896.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65310 -480 0 0 0 0 -12500000 -15000 0 0 0 0 0 0 -merge "cp_0/upbar" "io_analog[2]" -6942.45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55080 -460 0 0 0 0 -12500000 -15000 0 0 0 0 0 0 +merge "cp_1/gnd!" "vssa1" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0 +merge "vssa1" "ro_complete_0/w_7764_n10666#" +merge "ro_complete_0/w_7764_n10666#" "filter_0/v" +merge "filter_0/v" "divider_0/w_n966_n46#" +merge "divider_0/w_n966_n46#" "pd_0/w_n446_n1456#" +merge "pd_0/w_n446_n1456#" "cp_0/gnd!" +merge "cp_0/gnd!" "VSUBS" +merge "cp_1/down" "io_analog[1]" -8136.05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -173112 -2410 8212 -870 -227646 -1840 -12500000 -15000 0 0 0 0 0 0 +merge "cp_1/vbias" "io_analog[3]" -6896.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65310 -480 0 0 0 0 -12500000 -15000 0 0 0 0 0 0 +merge "cp_1/upbar" "io_analog[2]" -6942.45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55080 -460 0 0 0 0 -12500000 -15000 0 0 0 0 0 0 +merge "cp_1/out" "io_analog[0]" -3017.14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 148470 -1462 0 0 -4960000 -6468 0 0 0 0 0 0
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds index fa44b6f..3215525 100644 --- a/gds/user_analog_project_wrapper.gds +++ b/gds/user_analog_project_wrapper.gds Binary files differ
diff --git a/mag/and.ext b/mag/and.ext index ff013f3..81972f1 100644 --- a/mag/and.ext +++ b/mag/and.ext
@@ -1,4 +1,4 @@ -timestamp 1640957762 +timestamp 1640957225 version 8.3 tech sky130A style ngspice() @@ -17,25 +17,25 @@ substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap "gnd!" "Z1" 409.78 cap "OUT" "Z1" 43.6452 +cap "VDD" "OUT" 2.3125 cap "OUT" "gnd!" 198 cap "B" "Z1" 67.1786 cap "A" "gnd!" 57.75 cap "B" "OUT" 8.8 cap "vdd!" "Z1" 7.96552 +cap "VDD" "vdd!" 48.86 cap "out1" "Z1" 356.371 cap "vdd!" "gnd!" 13.8886 +cap "VDD" "out1" 6.1975 cap "out1" "gnd!" 226.769 cap "vdd!" "OUT" 574.768 cap "A" "B" 87.6201 cap "out1" "OUT" 261.752 cap "vdd!" "B" 13.5882 cap "vdd!" "A" 13.5882 -cap "VDD" "OUT" 2.3125 cap "out1" "B" 176.792 cap "out1" "A" 13.5179 cap "out1" "vdd!" 1441.54 -cap "VDD" "vdd!" 48.86 -cap "VDD" "out1" 6.1975 device msubckt sky130_fd_pr__nfet_01v8 480 -670 481 -669 l=30 w=300 "VSUBS" "out1" 60 0 "gnd!" 300 0 "OUT" 300 0 device msubckt sky130_fd_pr__nfet_01v8 230 -670 231 -669 l=30 w=400 "VSUBS" "B" 60 0 "Z1" 400 0 "out1" 400 0 device msubckt sky130_fd_pr__nfet_01v8 -20 -670 -19 -669 l=30 w=400 "VSUBS" "A" 60 0 "gnd!" 400 0 "Z1" 400 0
diff --git a/mag/and_pd.ext b/mag/and_pd.ext index 158d8cd..3fe6c54 100644 --- a/mag/and_pd.ext +++ b/mag/and_pd.ext
@@ -1,4 +1,4 @@ -timestamp 1640958486 +timestamp 1640776259 version 8.3 tech sky130A style ngspice() @@ -16,9 +16,6 @@ node "VDD" 2352 1494 -160 -70 nw 0 0 0 0 498000 2860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap "GND" "Z1" 192.37 -cap "VDD" "Out" 1.85 -cap "VDD" "a_n60_n30#" 37.17 -cap "VDD" "Out1" 3.7 cap "Out" "Z1" 19.8 cap "Out" "GND" 118.8 cap "a_n60_n30#" "Z1" 8.88462 @@ -26,15 +23,18 @@ cap "a_n60_n30#" "GND" 17.7692 cap "Out1" "GND" 176.55 cap "B" "Z1" 57.75 -cap "A" "GND" 57.75 cap "a_n60_n30#" "Out" 277.2 cap "Out1" "Out" 188.1 cap "B" "Out" 8.8 +cap "A" "GND" 57.75 cap "Out1" "a_n60_n30#" 1023.37 cap "B" "a_n60_n30#" 18.7 +cap "VDD" "Out" 1.85 cap "B" "Out1" 271.254 cap "A" "a_n60_n30#" 18.7 +cap "VDD" "a_n60_n30#" 37.17 cap "A" "Out1" 13.5179 +cap "VDD" "Out1" 3.7 cap "A" "B" 75.0211 device msubckt sky130_fd_pr__nfet_01v8 520 -470 521 -469 l=30 w=180 "VSUBS" "Out1" 60 0 "GND" 180 0 "Out" 180 0 device msubckt sky130_fd_pr__nfet_01v8 270 -470 271 -469 l=30 w=180 "VSUBS" "B" 60 0 "Z1" 180 0 "Out1" 180 0
diff --git a/mag/cbank.ext b/mag/cbank.ext index 14f11b3..0b0597d 100644 --- a/mag/cbank.ext +++ b/mag/cbank.ext
@@ -1,4 +1,4 @@ -timestamp 1640901595 +timestamp 1640959832 version 8.3 tech sky130A style ngspice() @@ -25,19 +25,19 @@ node "a_3680_n30#" 133 1402.86 3680 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0 node "a_2730_n30#" 133 1402.86 2730 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19600 560 19600 560 19600 560 642800 4060 0 0 0 0 0 0 node "a_1720_n30#" 120 0 1720 -30 ndif 0 0 0 0 0 0 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -substrate "gnd!" 0 0 4850 -1660 ppd 0 0 0 0 0 0 0 0 0 0 67600 1040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 455200 8040 376200 6460 439200 7160 1906800 11780 2795480 19244 0 0 0 0 +substrate "gnd!" 0 0 950 -1660 ppd 0 0 0 0 0 0 0 0 0 0 135200 2080 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 512800 9000 433800 7420 496800 8120 1964400 12740 2795480 19244 0 0 0 0 +cap "a_4660_n30#" "a_5640_n30#" 199.5 cap "a_2730_n30#" "v" 1301.39 +cap "a_3680_n30#" "a_4660_n30#" 199.5 +cap "a_2730_n30#" "li_1720_n30#" 199.5 cap "a_2730_n30#" "a_3680_n30#" 199.5 -cap "v" "li_1720_n30#" 1301.39 +cap "a_1720_n30#" "li_1720_n30#" 18.13 cap "a_6660_n30#" "v" 1301.39 cap "a_5640_n30#" "v" 1301.39 +cap "v" "li_1720_n30#" 1301.39 cap "a_5640_n30#" "a_6660_n30#" 191.52 cap "a_4660_n30#" "v" 1301.39 cap "a_3680_n30#" "v" 1301.39 -cap "a_4660_n30#" "a_5640_n30#" 199.5 -cap "a_3680_n30#" "a_4660_n30#" 199.5 -cap "a_2730_n30#" "li_1720_n30#" 199.5 -cap "a_1720_n30#" "li_1720_n30#" 18.13 device csubckt sky130_fd_pr__cap_mim_m3_1 6510 590 6511 591 w=560 l=560 "None" "v" 1920 0 "a_6660_n30#" 1440 0 device csubckt sky130_fd_pr__cap_mim_m3_1 5510 590 5511 591 w=560 l=560 "None" "v" 1920 0 "a_5640_n30#" 1440 0 device csubckt sky130_fd_pr__cap_mim_m3_1 4520 590 4521 591 w=560 l=560 "None" "v" 1920 0 "a_4660_n30#" 1440 0 @@ -45,20 +45,20 @@ device csubckt sky130_fd_pr__cap_mim_m3_1 2540 590 2541 591 w=560 l=560 "None" "v" 1920 0 "a_2730_n30#" 1440 0 device csubckt sky130_fd_pr__cap_mim_m3_1 1550 590 1551 591 w=560 l=560 "None" "v" 1920 0 "li_1720_n30#" 1440 0 device csubckt sky130_fd_pr__cap_mim_m3_1 70 130 71 131 w=1040 l=1000 "None" "v" 3760 0 "gnd!" 1440 0 -cap "switch_1/vin" "switch_1/vout" -0.157143 -cap "switch_1/vcont" "switch_1/vin" -136.5 cap "switch_0/vcont" "switch_0/vout" 4.23077 cap "switch_0/vcont" "switch_0/vin" 83.635 -cap "switch_2/vcont" "switch_2/vout" 4.23077 -cap "switch_2/vcont" "switch_2/vin" 83.635 -cap "switch_1/vcont" "switch_1/vout" 4.23077 +cap "switch_1/vin" "switch_1/vout" -0.157143 +cap "switch_1/vcont" "switch_1/vin" -136.5 +cap "switch_2/vout" "switch_2/vcont" 4.23077 +cap "switch_2/vin" "switch_2/vcont" 83.635 +cap "switch_1/vout" "switch_1/vcont" 4.23077 cap "switch_1/vcont" "switch_1/vin" 83.635 cap "switch_3/vcont" "switch_3/vout" 4.23077 cap "switch_3/vcont" "switch_3/vin" 83.635 -cap "switch_5/vcont" "switch_5/vout" 4.23077 -cap "switch_5/vcont" "switch_5/vin" 83.635 cap "switch_4/vcont" "switch_4/vout" 4.23077 cap "switch_4/vcont" "switch_4/vin" 83.635 +cap "switch_5/vout" "switch_5/vcont" 4.23077 +cap "switch_5/vin" "switch_5/vcont" 83.635 merge "switch_5/VSUBS" "switch_5/vout" -332.789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -280 -1316 0 0 0 0 0 0 -21300 -442 0 0 0 0 merge "switch_5/vout" "switch_4/VSUBS" merge "switch_4/VSUBS" "switch_4/vout"
diff --git a/mag/cbank.mag b/mag/cbank.mag index 9b6d72f..b36ac80 100644 --- a/mag/cbank.mag +++ b/mag/cbank.mag
@@ -1,9 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1640901595 -<< error_s >> -rect 1700 -1308 1880 132 +timestamp 1640959530 << ndiff >> rect 1720 -30 1860 110 rect 2730 92 2870 110 @@ -33,11 +31,16 @@ rect 5660 -8 5760 92 rect 6680 -8 6780 92 << psubdiff >> +rect 950 -1430 1210 -1400 +rect 950 -1630 980 -1430 +rect 1180 -1630 1210 -1430 +rect 950 -1660 1210 -1630 rect 4850 -1430 5110 -1400 rect 4850 -1630 4880 -1430 rect 5080 -1630 5110 -1430 rect 4850 -1660 5110 -1630 << psubdiffcont >> +rect 980 -1630 1180 -1430 rect 4880 -1630 5080 -1430 << locali >> rect 40 1520 230 1540 @@ -85,6 +88,10 @@ rect 4930 -1410 5030 -1280 rect 5910 -1410 6010 -1280 rect 6930 -1410 7030 -1280 +rect 960 -1430 1200 -1410 +rect 960 -1630 980 -1430 +rect 1180 -1630 1200 -1430 +rect 960 -1650 1200 -1630 rect 1920 -1430 2160 -1410 rect 1920 -1630 1940 -1430 rect 2140 -1630 2160 -1430 @@ -123,6 +130,7 @@ rect 5660 -10 5760 -8 rect 6680 -8 6780 90 rect 6680 -10 6780 -8 +rect 980 -1630 1180 -1430 rect 1940 -1630 2140 -1430 rect 2950 -1630 3150 -1430 rect 3900 -1630 4100 -1430 @@ -162,6 +170,10 @@ rect 6780 -10 6800 90 rect 6660 -30 6800 -10 rect 500 -160 680 -140 +rect 960 -1430 1200 -1410 +rect 960 -1630 980 -1430 +rect 1180 -1630 1200 -1430 +rect 960 -1650 1200 -1630 rect 1920 -1430 2160 -1410 rect 1920 -1630 1940 -1430 rect 2140 -1630 2160 -1430 @@ -195,6 +207,7 @@ rect 4680 -10 4780 90 rect 5660 -10 5760 90 rect 6680 -10 6780 90 +rect 980 -1630 1180 -1430 rect 1940 -1630 2140 -1430 rect 2950 -1630 3150 -1430 rect 3900 -1630 4100 -1430 @@ -237,6 +250,10 @@ rect 500 -490 520 -350 rect 660 -490 680 -350 rect 500 -510 680 -490 +rect 960 -1430 1200 -1410 +rect 960 -1630 980 -1430 +rect 1180 -1630 1200 -1430 +rect 960 -1650 1200 -1630 rect 1920 -1430 2160 -1410 rect 1920 -1630 1940 -1430 rect 2140 -1630 2160 -1430 @@ -271,6 +288,7 @@ rect 5660 -10 5760 90 rect 6680 -10 6780 90 rect 520 -490 660 -350 +rect 980 -1630 1180 -1430 rect 1940 -1630 2140 -1430 rect 2950 -1630 3150 -1430 rect 3900 -1630 4100 -1430 @@ -321,6 +339,10 @@ rect 500 -490 520 -350 rect 660 -490 680 -350 rect 500 -510 680 -490 +rect 960 -1430 1200 -1410 +rect 960 -1630 980 -1430 +rect 1180 -1630 1200 -1430 +rect 960 -1650 1200 -1630 rect 1920 -1430 2160 -1410 rect 1920 -1630 1940 -1430 rect 2140 -1630 2160 -1430 @@ -348,6 +370,7 @@ << via3 >> rect 60 1370 210 1520 rect 520 -490 660 -350 +rect 980 -1630 1180 -1430 rect 1940 -1630 2140 -1430 rect 2950 -1630 3150 -1430 rect 3900 -1630 4100 -1430 @@ -440,7 +463,8 @@ rect 760 -542 1230 -540 rect 930 -1380 1230 -542 rect 930 -1430 8150 -1380 -rect 930 -1630 1940 -1430 +rect 930 -1630 980 -1430 +rect 1180 -1630 1940 -1430 rect 2140 -1630 2950 -1430 rect 3150 -1630 3900 -1430 rect 4100 -1630 4880 -1430 @@ -448,29 +472,29 @@ rect 6060 -1630 6890 -1430 rect 7090 -1630 8150 -1430 rect 930 -1680 8150 -1630 -use switch switch_5 -timestamp 1640608635 -transform 1 0 6830 0 1 -1308 -box -190 -40 240 1600 -use switch switch_4 -timestamp 1640608635 -transform 1 0 5810 0 1 -1308 -box -190 -40 240 1600 -use switch switch_3 -timestamp 1640608635 -transform 1 0 4830 0 1 -1308 -box -190 -40 240 1600 -use switch switch_2 -timestamp 1640608635 -transform 1 0 3850 0 1 -1308 +use switch switch_0 +timestamp 1640959530 +transform 1 0 1890 0 1 -1308 box -190 -40 240 1600 use switch switch_1 -timestamp 1640608635 +timestamp 1640959530 transform 1 0 2900 0 1 -1308 box -190 -40 240 1600 -use switch switch_0 -timestamp 1640608635 -transform 1 0 1890 0 1 -1308 +use switch switch_2 +timestamp 1640959530 +transform 1 0 3850 0 1 -1308 +box -190 -40 240 1600 +use switch switch_3 +timestamp 1640959530 +transform 1 0 4830 0 1 -1308 +box -190 -40 240 1600 +use switch switch_4 +timestamp 1640959530 +transform 1 0 5810 0 1 -1308 +box -190 -40 240 1600 +use switch switch_5 +timestamp 1640959530 +transform 1 0 6830 0 1 -1308 box -190 -40 240 1600 << labels >> rlabel locali 20 1360 20 1360 1 v
diff --git a/mag/cp.ext b/mag/cp.ext index b9bda49..d02f0a3 100644 --- a/mag/cp.ext +++ b/mag/cp.ext
@@ -1,4 +1,4 @@ -timestamp 1640911630 +timestamp 1640911461 version 8.3 tech sky130A style ngspice() @@ -20,23 +20,23 @@ node "upbar" 658 1347.77 6750 -50 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1444800 9060 0 0 126800 2040 0 0 0 0 0 0 0 0 0 0 0 0 node "vdd!" 18302 139352 -830 -170 nw 0 0 0 0 43093400 28900 0 0 704700 10080 5472000 31840 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 745200 5020 0 0 5560800 43900 1430500 20260 818100 12540 818100 12540 6272200 36660 0 0 0 0 substrate "gnd!" 0 0 -370 -2840 ndif 0 0 0 0 0 0 0 0 3419400 21800 243600 3420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1389600 8600 0 0 3637300 30060 802800 10020 421200 6360 421200 6360 4550400 19920 0 0 0 0 -cap "a_10_n50#" "vbias" 192.9 -cap "vdd!" "a_7110_0#" 42.55 -cap "out" "a_1710_0#" 841.733 -cap "a_1710_n2840#" "a_1710_0#" 828.847 -cap "a_10_n50#" "a_1710_0#" 41.6842 -cap "vdd!" "a_6370_0#" 402.828 -cap "a_1710_n2840#" "out" 606.81 -cap "vdd!" "a_3060_0#" 1788.27 -cap "vdd!" "a_1710_0#" 714.147 -cap "vdd!" "out" 376.075 cap "upbar" "a_1710_n2840#" 291.6 cap "vdd!" "a_1710_n2840#" 254.08 cap "vdd!" "a_10_n50#" 530.297 +cap "a_10_n50#" "vbias" 192.9 cap "vdd!" "upbar" 149.92 -cap "a_1710_0#" "down" 320.4 +cap "a_1710_n2840#" "a_1710_0#" 828.847 +cap "a_10_n50#" "a_1710_0#" 41.6842 +cap "a_1710_n2840#" "out" 606.81 cap "vdd!" "a_3060_n2840#" 320.4 cap "upbar" "down" 20.625 +cap "vdd!" "a_7110_0#" 42.55 +cap "vdd!" "a_6370_0#" 402.828 +cap "vdd!" "a_3060_0#" 1788.27 +cap "vdd!" "a_1710_0#" 714.147 +cap "vdd!" "out" 376.075 +cap "a_1710_0#" "down" 320.4 +cap "out" "a_1710_0#" 841.733 device msubckt sky130_fd_pr__nfet_01v8 8100 -2840 8101 -2839 l=360 w=1800 "gnd!" "a_1710_0#" 720 0 "a_7110_n2840#" 1800 0 "out" 1800 0 device msubckt sky130_fd_pr__nfet_01v8 6750 -2840 6751 -2839 l=360 w=1800 "gnd!" "down" 720 0 "gnd!" 1800 0 "a_7110_n2840#" 1800 0 device msubckt sky130_fd_pr__nfet_01v8 5400 -2840 5401 -2839 l=360 w=1800 "gnd!" "out" 720 0 "a_3060_n2840#" 1800 0 "gnd!" 1800 0
diff --git a/mag/divider.ext b/mag/divider.ext index a5216e4..9dc9e59 100644 --- a/mag/divider.ext +++ b/mag/divider.ext
@@ -4,13 +4,13 @@ style ngspice() scale 1000 1 500000 resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 -use nor nor_0 -1 0 5660 0 -1 3210 -use nor nor_1 -1 0 6630 0 -1 3210 -use and and_0 -1 0 4660 0 -1 2930 -use prescaler prescaler_0 1 0 50 0 1 400 use tspc tspc_2 1 0 7280 0 1 990 use tspc tspc_1 1 0 5700 0 1 990 use tspc tspc_0 1 0 4120 0 1 990 +use prescaler prescaler_0 1 0 50 0 1 400 +use and and_0 -1 0 4660 0 -1 2930 +use nor nor_0 -1 0 5660 0 -1 3210 +use nor nor_1 -1 0 6630 0 -1 3210 node "m4_7020_30#" 0 79.26 7020 30 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 480 0 0 0 0 node "gnd" 0 83.08 5430 30 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11400 500 0 0 0 0 node "gnd" 0 79.08 3830 30 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10800 480 0 0 0 0 @@ -40,242 +40,242 @@ node "w_n140_1520#" 3438 3270.42 -140 1520 nw 0 0 0 0 1008000 4240 0 0 122500 1400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67080 1036 67080 1036 67080 1036 67080 1036 168928 2064 0 0 0 0 node "w_2780_1920#" 31943 20273.1 2780 1920 nw 0 0 0 0 6485992 23000 0 0 245000 2800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 134160 2072 134160 2072 134160 2072 134160 2072 610588 4880 0 0 0 0 substrate "a_n940_n20#" 0 0 -940 -20 ppd 0 0 0 0 0 0 0 0 0 0 1757600 27040 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9826000 57800 0 0 0 0 0 0 0 0 0 0 0 0 -cap "li_5560_680#" "m4_7020_30#" 24.425 -cap "w_2780_1920#" "vdd" 8.88 -cap "mc2" "gnd" 27.9 -cap "li_3980_680#" "gnd" 24.425 -cap "li_3980_680#" "gnd" 27.1625 cap "mc2" "m1_5770_3360#" 35.7143 cap "mc2" "li_7140_680#" 61.52 -cap "w_2780_1920#" "m1_5770_3360#" 53.84 -cap "li_5740_3250#" "vdd" 27.9 -cap "li_3310_1810#" "vdd" 35.39 -cap "li_5740_3250#" "vdd" 27.9 -cap "mc2" "li_5740_3250#" 22.679 -cap "w_2780_1920#" "li_3310_1810#" 24.0375 -cap "w_2780_1920#" "li_5740_3250#" 72.945 -cap "w_2780_1920#" "li_6130_3350#" 7.215 cap "li_7140_680#" "m1_5770_3360#" 19.2857 cap "li_5560_680#" "m1_5770_3360#" 16.875 cap "li_5560_680#" "li_7140_680#" 437.5 cap "li_7040_820#" "m1_5770_3360#" 90 cap "li_3980_680#" "li_5560_680#" 782.5 cap "Out" "li_7140_680#" 23.5 +cap "mc2" "li_5740_3250#" 22.679 +cap "gnd" "li_3980_680#" 24.425 cap "li_7040_820#" "li_5560_680#" 15 +cap "gnd" "li_3980_680#" 27.1625 cap "li_5740_3250#" "m1_5770_3360#" 286.375 cap "li_5460_820#" "li_3980_680#" 20 cap "li_6130_3350#" "m1_5770_3360#" 136.842 cap "li_5740_3250#" "li_5560_680#" 21.9534 -cap "w_2780_1920#" "m4_7030_1860#" 40.0711 +cap "gnd" "mc2" 27.9 cap "li_5740_3250#" "li_3980_680#" 22.5 -cap "w_2780_1920#" "vdd" 0.84 -cap "w_2780_1920#" "vdd" 9.82 -cap "w_2780_1920#" "li_2870_2670#" 76.8485 -cap "w_2780_1920#" "vdd" 4.08 cap "li_5740_3250#" "li_5460_820#" 128.305 -cap "li_6130_3350#" "li_5740_3250#" 68.1032 +cap "vdd" "li_5740_3250#" 27.9 +cap "vdd" "li_3310_1810#" 35.39 cap "vdd" "vdd" 33.5 +cap "vdd" "li_5740_3250#" 27.9 +cap "li_6130_3350#" "li_5740_3250#" 68.1032 cap "vdd" "vdd" 51.2353 cap "vdd" "vdd" 20.1 +cap "w_2780_1920#" "li_2870_2670#" 76.8485 +cap "w_2780_1920#" "m1_5770_3360#" 53.84 +cap "w_2780_1920#" "m4_7030_1860#" 40.0711 +cap "m4_7020_30#" "li_5560_680#" 24.425 +cap "w_2780_1920#" "vdd" 0.84 +cap "w_2780_1920#" "li_3310_1810#" 24.0375 +cap "w_2780_1920#" "vdd" 9.82 +cap "w_2780_1920#" "li_5740_3250#" 72.945 +cap "w_2780_1920#" "vdd" 4.08 +cap "w_2780_1920#" "li_6130_3350#" 7.215 +cap "w_2780_1920#" "vdd" 8.88 cap "a_n940_n20#" "prescaler_0/nand_0/A" 17.3684 -cap "a_n940_n20#" "prescaler_0/tspc_0/a_630_n680#" 9.78378 -cap "a_n940_n20#" "prescaler_0/GND" 21.945 -cap "a_n940_n20#" "prescaler_0/tspc_0/Z2" 27.6618 +cap "prescaler_0/tspc_0/a_630_n680#" "a_n940_n20#" 9.78378 +cap "prescaler_0/GND" "a_n940_n20#" 21.945 +cap "prescaler_0/tspc_0/Z2" "a_n940_n20#" 27.6618 cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189 cap "a_n940_n20#" "prescaler_0/tspc_1/Z2" 27.6618 cap "a_n940_n20#" "prescaler_0/tspc_1/GND" 30.14 -cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375 -cap "tspc_0/w_n140_n70#" "prescaler_0/GND" 0.12 -cap "a_n940_n20#" "prescaler_0/GND" 21.945 -cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189 -cap "tspc_0/D" "tspc_0/Z4" 35.0633 -cap "tspc_0/D" "tspc_0/Z2" 141.466 -cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195 -cap "tspc_0/D" "prescaler_0/GND" 413.181 -cap "a_n940_n20#" "tspc_0/Z2" 27.6618 +cap "a_n940_n20#" "tspc_0/GND" 21.945 +cap "tspc_0/Z4" "tspc_0/D" 35.0633 +cap "tspc_0/GND" "tspc_0/a_300_n150#" -3.55271e-15 +cap "tspc_0/Z2" "tspc_0/D" 141.466 +cap "tspc_0/GND" "tspc_0/D" 413.181 cap "tspc_0/D" "tspc_0/Z3" 1.36364 +cap "tspc_0/GND" "tspc_0/w_n140_n70#" 0.12 +cap "prescaler_0/tspc_1/a_740_n680#" "tspc_0/D" 8.4375 cap "prescaler_0/tspc_1/Q" "tspc_0/D" 25.3985 -cap "tspc_0/a_740_n680#" "tspc_1/D" -7.31795 -cap "tspc_1/a_300_n150#" "tspc_1/D" 70.641 -cap "tspc_1/GND" "tspc_0/a_630_n680#" 7.61538 -cap "tspc_0/a_740_n680#" "tspc_1/a_300_n150#" 145.525 -cap "tspc_1/D" "tspc_1/Z2" 213.298 -cap "tspc_1/D" "tspc_1/Z4" 33.0938 -cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823 -cap "tspc_1/a_300_n150#" "tspc_1/Z4" 30.4615 -cap "tspc_1/a_300_n150#" "tspc_1/Z2" 25.8231 -cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714 -cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065 -cap "tspc_1/w_n140_n70#" "tspc_1/a_300_n150#" 2.77556e-17 -cap "a_n940_n20#" "tspc_1/Z2" 27.6618 +cap "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/a_740_n680#" 0.195 +cap "a_n940_n20#" "tspc_0/Z2" 27.6618 +cap "a_n940_n20#" "prescaler_0/tspc_1/a_630_n680#" 4.89189 cap "tspc_1/D" "tspc_0/a_630_n680#" 5.45455 cap "tspc_1/D" "tspc_1/GND" 346.096 cap "tspc_0/a_740_n680#" "tspc_0/a_630_n680#" 159.583 cap "tspc_1/a_300_n150#" "tspc_1/GND" 21.2143 -cap "tspc_0/a_740_n680#" "tspc_1/GND" 281.141 cap "tspc_1/D" "tspc_1/Z3" 1.36364 +cap "tspc_0/a_740_n680#" "tspc_1/GND" 281.141 +cap "tspc_1/a_300_n150#" "tspc_1/D" 70.641 +cap "tspc_0/a_740_n680#" "tspc_1/D" -7.31795 +cap "a_n940_n20#" "tspc_1/Z2" 27.6618 +cap "tspc_0/a_740_n680#" "tspc_1/a_300_n150#" 145.525 cap "tspc_1/GND" "tspc_1/Z2" 7.81579 -cap "a_n940_n20#" "tspc_1/GND" 23.265 +cap "tspc_1/w_n140_n70#" "tspc_1/a_300_n150#" 2.77556e-17 +cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 0.065 +cap "tspc_1/D" "tspc_1/Z4" 33.0938 +cap "tspc_1/D" "tspc_1/Z2" 213.298 cap "a_n940_n20#" "tspc_0/a_630_n680#" 9.78378 -cap "tspc_1/a_740_n680#" "tspc_2/gnd!" 440.385 -cap "tspc_2/a_300_n150#" "tspc_2/D" 70.641 -cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619 -cap "tspc_1/a_740_n680#" "tspc_2/a_300_n150#" 155.525 -cap "tspc_2/w_n140_n70#" "tspc_1/a_740_n680#" 0.065 +cap "tspc_1/a_300_n150#" "tspc_1/Z4" 30.4615 +cap "tspc_0/a_740_n680#" "tspc_1/Z4" 20.5714 +cap "tspc_0/a_740_n680#" "tspc_1/Z2" 112.823 +cap "a_n940_n20#" "tspc_1/GND" 23.265 +cap "tspc_1/a_300_n150#" "tspc_1/Z2" 25.8231 +cap "tspc_1/GND" "tspc_0/a_630_n680#" 7.61538 cap "tspc_2/gnd!" "tspc_2/Z2" 7.81579 -cap "a_n940_n20#" "tspc_2/Z2" 12.6176 cap "tspc_2/D" "tspc_2/Z3" 0.681818 cap "tspc_2/D" "tspc_2/Z4" 20.0553 -cap "tspc_2/a_300_n150#" "tspc_2/Z4" 30.4615 cap "tspc_2/D" "tspc_2/Z2" 309.898 +cap "tspc_2/a_300_n150#" "tspc_2/Z4" 30.4615 cap "tspc_1/a_740_n680#" "tspc_2/Z4" 10.5882 -cap "tspc_2/a_300_n150#" "tspc_2/Z2" 25.8231 cap "tspc_1/a_740_n680#" "tspc_2/Z2" 116.18 +cap "tspc_2/a_300_n150#" "tspc_2/Z2" 25.8231 +cap "a_n940_n20#" "tspc_2/Z2" 12.6176 cap "tspc_2/gnd!" "tspc_1/a_630_n680#" 7.61538 -cap "a_n940_n20#" "tspc_1/a_630_n680#" 9.78378 -cap "a_n940_n20#" "tspc_2/gnd!" 30.14 cap "tspc_2/D" "tspc_1/a_630_n680#" 1.21622 cap "tspc_2/D" "tspc_2/gnd!" 339.551 cap "tspc_1/a_740_n680#" "tspc_1/a_630_n680#" 159.107 cap "tspc_2/a_300_n150#" "tspc_2/gnd!" 21.2143 +cap "tspc_1/a_740_n680#" "tspc_2/gnd!" 440.385 +cap "tspc_2/w_n140_n70#" "tspc_1/a_740_n680#" 0.065 +cap "tspc_2/a_300_n150#" "tspc_2/D" 70.641 +cap "a_n940_n20#" "tspc_1/a_630_n680#" 9.78378 +cap "tspc_1/a_740_n680#" "tspc_2/D" -6.57619 +cap "a_n940_n20#" "tspc_2/gnd!" 30.14 +cap "tspc_1/a_740_n680#" "tspc_2/a_300_n150#" 155.525 +cap "tspc_2/D" "tspc_2/a_630_n680#" 159.583 +cap "tspc_2/D" "tspc_2/GND" 450.398 +cap "tspc_2/D" "tspc_2/Z4" 17.815 +cap "tspc_2/Z4" "li_5560_680#" 10.5882 +cap "a_n940_n20#" "tspc_2/GND" 23.265 +cap "a_n940_n20#" "tspc_2/a_630_n680#" 9.78378 +cap "tspc_2/D" "tspc_2/Q" 20.775 +cap "a_n940_n20#" "tspc_2/Z2" 15.0441 cap "tspc_2/D" "tspc_2/Z3" 0.681818 cap "tspc_2/D" "tspc_2/a_300_n150#" -1.77636e-15 -cap "tspc_2/a_630_n680#" "tspc_2/D" 159.583 -cap "tspc_2/GND" "tspc_2/D" 450.398 -cap "tspc_2/Z4" "tspc_2/D" 17.815 -cap "tspc_2/GND" "a_n940_n20#" 23.265 -cap "tspc_2/a_630_n680#" "a_n940_n20#" 9.78378 -cap "tspc_2/Z2" "a_n940_n20#" 15.0441 -cap "tspc_2/Z4" "li_5560_680#" 10.5882 -cap "tspc_2/D" "tspc_2/Q" 20.775 -cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 78.0797 -cap "prescaler_0/nand_0/A" "prescaler_0/nand_0/VDD" 12.2938 -cap "prescaler_0/nand_0/A" "a_n940_n20#" 14.7632 -cap "prescaler_0/tspc_0/D" "prescaler_0/nand_0/VDD" -2.84217e-14 +cap "prescaler_0/nand_0/VDD" "prescaler_0/nand_0/A" 12.2938 +cap "a_n940_n20#" "prescaler_0/nand_0/A" 14.7632 cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/vdd!" 4.57853 cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/Q" 6.67557 -cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z1" -2.4869e-14 -cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_2/Q" 6.67557 +cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 78.0797 cap "prescaler_0/tspc_0/Z2" "prescaler_0/nand_0/VDD" -1.77636e-15 cap "prescaler_0/mc1" "prescaler_0/nand_0/VDD" 2.73 +cap "prescaler_0/tspc_2/Q" "prescaler_0/nand_0/VDD" 6.67557 +cap "prescaler_0/nand_0/VDD" "prescaler_0/tspc_0/Z1" -2.4869e-14 +cap "prescaler_0/tspc_1/vdd!" "prescaler_0/mc1" 73.8879 cap "prescaler_0/tspc_1/Z3" "prescaler_0/tspc_1/vdd!" -2.37588e-14 -cap "prescaler_0/tspc_1/Z2" "prescaler_0/tspc_1/vdd!" 6.92779e-14 -cap "prescaler_0/tspc_1/Z1" "prescaler_0/tspc_1/vdd!" 3.19744e-14 -cap "prescaler_0/mc1" "prescaler_0/tspc_1/vdd!" 73.8879 -cap "prescaler_0/nand_1/a_280_n230#" "prescaler_0/tspc_1/vdd!" 14.3654 -cap "and_0/VDD" "and_0/OUT" 7.5 -cap "and_0/VDD" "prescaler_0/GND" 244.839 -cap "and_0/VDD" "prescaler_0/mc1" 2.6129 -cap "and_0/VDD" "tspc_0/Z1" -2.4869e-14 -cap "and_0/VDD" "tspc_0/Z2" 10 -cap "and_0/VDD" "prescaler_0/tspc_1/Q" 19.25 -cap "and_0/VDD" "prescaler_0/tspc_1/a_740_n680#" 114.95 -cap "nor_0/vdd!" "tspc_1/a_300_n150#" 93.7845 +cap "prescaler_0/tspc_1/vdd!" "prescaler_0/nand_1/a_280_n230#" 14.3654 +cap "prescaler_0/tspc_1/vdd!" "prescaler_0/tspc_1/Z1" 3.19744e-14 +cap "prescaler_0/tspc_1/vdd!" "prescaler_0/tspc_1/Z2" 6.92779e-14 +cap "tspc_0/vdd!" "prescaler_0/GND" 244.839 +cap "tspc_0/vdd!" "prescaler_0/mc1" 2.6129 +cap "tspc_0/vdd!" "tspc_0/Z2" 10 +cap "tspc_0/vdd!" "prescaler_0/tspc_1/Q" 19.25 +cap "tspc_0/vdd!" "prescaler_0/tspc_1/a_740_n680#" 114.95 +cap "tspc_0/vdd!" "and_0/OUT" 7.5 +cap "tspc_1/w_n140_n70#" "tspc_1/vdd!" -3.46 cap "tspc_1/a_300_n150#" "tspc_1/Z1" 7 -cap "nor_0/vdd!" "tspc_0/a_740_n680#" 177.528 -cap "nor_0/VDD" "tspc_0/a_740_n680#" 4.63 cap "tspc_0/a_740_n680#" "tspc_1/Z2" 41.1927 -cap "nor_0/VDD" "nor_0/vdd!" -3.46 +cap "tspc_1/vdd!" "tspc_1/a_300_n150#" 93.7845 +cap "tspc_1/w_n140_n70#" "tspc_0/a_740_n680#" 4.63 +cap "tspc_1/vdd!" "tspc_0/a_740_n680#" 177.528 cap "tspc_0/a_740_n680#" "tspc_1/a_300_n150#" 75.365 -cap "nor_0/VDD" "tspc_1/Z2" 3.10862e-14 -cap "nor_0/vdd!" "tspc_1/a_740_n680#" 13.3333 -cap "nor_0/VDD" "tspc_1/a_740_n680#" 76.5957 -cap "nor_0/VDD" "nor_0/vdd!" 224.245 -cap "tspc_2/Z1" "tspc_2/a_300_n150#" 7 -cap "tspc_2/Z2" "tspc_1/a_740_n680#" 85.1351 +cap "tspc_2/vdd!" "nor_0/vdd!" 224.245 +cap "tspc_1/a_740_n680#" "tspc_2/Z2" 85.1351 cap "tspc_1/a_740_n680#" "tspc_2/a_300_n150#" 75.365 -cap "tspc_2/Z2" "nor_0/VDD" 4.44089e-16 -cap "tspc_2/Z1" "nor_0/VDD" 2.2482e-14 -cap "nor_0/VDD" "tspc_1/Z3" -2.37588e-14 -cap "nor_0/VDD" "tspc_2/a_300_n150#" 93.7845 +cap "tspc_2/vdd!" "tspc_2/Z2" 4.44089e-16 +cap "tspc_2/vdd!" "tspc_2/Z1" 2.2482e-14 +cap "tspc_2/vdd!" "tspc_2/a_300_n150#" 93.7845 +cap "tspc_2/vdd!" "tspc_1/Z3" -2.37588e-14 +cap "tspc_2/vdd!" "tspc_1/Z2" 3.10862e-14 +cap "tspc_2/a_300_n150#" "tspc_2/Z1" 7 +cap "nor_0/vdd!" "tspc_1/a_740_n680#" 13.3333 +cap "tspc_2/vdd!" "tspc_1/a_740_n680#" 76.5957 cap "tspc_2/vdd!" "tspc_2/Q" -5.32907e-14 cap "tspc_2/vdd!" "tspc_2/Z3" -2.37588e-14 cap "tspc_2/vdd!" "tspc_2/Z2" 3.73035e-14 -cap "tspc_2/vdd!" "tspc_2/a_740_n680#" 13.125 cap "tspc_2/vdd!" "tspc_2/Z1" -1.90958e-14 +cap "tspc_2/vdd!" "tspc_2/a_740_n680#" 13.125 cap "w_n140_1520#" "prescaler_0/tspc_2/vdd!" 6.56545 cap "w_n140_1520#" "prescaler_0/tspc_2/Q" 27.2014 cap "prescaler_0/tspc_2/a_630_n680#" "mc2" 328.675 cap "prescaler_0/GND" "mc2" 319.267 -cap "a_n940_n20#" "prescaler_0/tspc_2/a_630_n680#" 5.04167 -cap "a_n940_n20#" "prescaler_0/GND" 12.1359 cap "prescaler_0/tspc_2/Z2" "mc2" 136.815 cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Z1" -2.84217e-14 -cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 9.75806 -cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Q" 9.57252 -cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/a_300_n150#" 5.55112e-16 -cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/Z3" -1.33227e-15 +cap "prescaler_0/tspc_2/a_630_n680#" "a_n940_n20#" 5.04167 +cap "prescaler_0/GND" "a_n940_n20#" 12.1359 +cap "prescaler_0/tspc_2/Q" "prescaler_0/tspc_2/vdd!" 9.57252 cap "prescaler_0/tspc_2/vdd!" "prescaler_0/tspc_2/a_740_n680#" -1.13687e-13 -cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/a_280_n230#" 34.0634 +cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 9.75806 +cap "prescaler_0/tspc_2/Z2" "mc2" -280.235 cap "prescaler_0/nand_1/VDD" "prescaler_0/mc1" 19.9143 +cap "prescaler_0/nand_1/VDD" "prescaler_0/nand_1/a_280_n230#" 34.0634 cap "a_n940_n20#" "prescaler_0/GND" 3.58696 cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/D" 1.13687e-13 +cap "prescaler_0/nand_1/VDD" "prescaler_0/tspc_2/Z2" 1.66533e-15 cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 4.5 cap "prescaler_0/GND" "mc2" 127.942 -cap "prescaler_0/tspc_2/Z2" "mc2" -280.235 -cap "mc2" "and_0/B" 13.94 -cap "mc2" "and_0/out1" 59.955 -cap "prescaler_0/m1_2700_2190#" "and_0/VDD" 36.6566 -cap "and_0/GND" "and_0/VDD" 23.0856 -cap "and_0/OUT" "and_0/out1" 48.6223 -cap "and_0/OUT" "and_0/VDD" 0.870968 +cap "and_0/out1" "prescaler_0/mc1" 48.6223 +cap "and_0/VDD" "prescaler_0/m1_2700_2190#" 36.6566 +cap "and_0/VDD" "prescaler_0/GND" 23.0856 +cap "a_n940_n20#" "and_0/Z1" 5.5 cap "and_0/Z1" "mc2" 74.215 -cap "and_0/GND" "mc2" 117.19 -cap "and_0/OUT" "mc2" 46.015 -cap "and_0/OUT" "and_0/vdd!" 39.6 -cap "and_0/OUT" "and_0/GND" 22.72 +cap "a_n940_n20#" "prescaler_0/GND" 5.09291 +cap "and_0/VDD" "prescaler_0/mc1" 0.870968 +cap "prescaler_0/mc1" "mc2" 46.015 +cap "a_n940_n20#" "prescaler_0/mc1" 3.20833 +cap "prescaler_0/GND" "mc2" 117.19 +cap "prescaler_0/mc1" "and_0/vdd!" 39.6 cap "a_n940_n20#" "and_0/out1" 3.20833 -cap "and_0/Z1" "a_n940_n20#" 5.5 -cap "and_0/GND" "a_n940_n20#" 5.09291 -cap "and_0/OUT" "a_n940_n20#" 3.20833 -cap "nor_0/B" "nor_0/A" 58.3333 -cap "nor_0/Out" "nor_0/B" 13.2 -cap "nor_1/Out" "nor_0/Z1" 181.56 -cap "nor_1/Out" "nor_0/vdd!" 90.78 -cap "a_n940_n20#" "and_0/Z1" 0.916667 -cap "nor_1/Out" "nor_0/A" 15.1125 -cap "a_n940_n20#" "nor_0/GND" 6.50362 -cap "nor_1/Out" "nor_0/B" 84.4673 -cap "nor_0/VDD" "nor_0/A" 0.99 -cap "nor_1/Out" "nor_0/Out" 90.78 -cap "a_n940_n20#" "nor_0/Out" 7 -cap "nor_0/VDD" "nor_1/Out" 4.29 +cap "and_0/B" "mc2" 13.94 +cap "and_0/out1" "mc2" 59.955 +cap "prescaler_0/mc1" "prescaler_0/GND" 22.72 cap "and_0/Z1" "mc2" -164.32 -cap "nor_0/GND" "mc2" 364.635 +cap "and_0/GND" "mc2" 364.635 cap "nor_0/A" "mc2" 12.84 cap "nor_0/B" "mc2" 12.84 -cap "nor_0/Out" "mc2" 161.385 -cap "nor_0/Out" "nor_0/Z1" 22.8782 -cap "nor_0/A" "nor_0/GND" 1.28205 +cap "and_0/GND" "and_0/vdd!" -8.88178e-16 +cap "and_0/A" "mc2" 161.385 +cap "and_0/A" "nor_0/Z1" 22.8782 +cap "and_0/B" "nor_0/Z1" 181.56 +cap "and_0/A" "and_0/vdd!" 5.32907e-15 +cap "and_0/B" "and_0/vdd!" 90.78 +cap "nor_0/A" "and_0/GND" 1.28205 cap "nor_0/B" "nor_1/B" 2.64706 -cap "nor_0/Out" "nor_0/GND" 16.9459 -cap "nor_0/vdd!" "nor_0/B" 90.78 -cap "nor_1/Z1" "nor_0/B" 181.56 -cap "nor_1/Out" "nor_0/B" 90.78 +cap "and_0/A" "and_0/GND" 16.9459 +cap "a_n940_n20#" "and_0/Z1" 0.916667 +cap "nor_0/B" "nor_0/A" 58.3333 +cap "and_0/B" "nor_0/A" 15.1125 +cap "a_n940_n20#" "and_0/GND" 6.50362 +cap "and_0/A" "nor_0/B" 13.2 +cap "and_0/B" "nor_0/B" 84.4673 +cap "and_0/VDD" "nor_0/A" 0.99 +cap "and_0/B" "and_0/A" 90.78 +cap "and_0/VDD" "and_0/B" 4.29 +cap "a_n940_n20#" "and_0/A" 7 cap "nor_1/A" "nor_0/B" 15.1125 -cap "nor_1/B" "nor_0/B" 17.7596 cap "nor_1/A" "nor_1/Out" 180.039 cap "nor_1/A" "nor_1/GND" 305.362 -cap "nor_1/B" "nor_1/Out" 41.7957 -cap "nor_1/B" "nor_1/A" 14.5768 -cap "nor_0/VDD" "nor_0/B" -7.41 -cap "nor_0/VDD" "nor_1/Out" 4.29 -cap "a_n940_n20#" "nor_1/Out" 7 cap "a_n940_n20#" "nor_1/GND" 2 +cap "a_n940_n20#" "nor_1/Out" 7 +cap "nor_1/B" "nor_0/B" 17.7596 +cap "nor_0/VDD" "nor_0/B" -7.41 +cap "nor_1/B" "nor_1/Out" 41.7957 +cap "nor_0/VDD" "nor_1/Out" 4.29 +cap "nor_1/B" "nor_1/A" 14.5768 +cap "nor_1/Z1" "nor_0/B" 181.56 +cap "nor_0/vdd!" "nor_0/B" 90.78 +cap "nor_1/Out" "nor_0/B" 90.78 cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 9.75806 cap "a_n940_n20#" "prescaler_0/tspc_2/a_630_n680#" 5.04167 cap "a_n940_n20#" "prescaler_0/GND" 12.1359 -cap "a_n940_n20#" "prescaler_0/GND" 3.58696 cap "a_n940_n20#" "prescaler_0/tspc_2/Z2" 4.5 -cap "a_n940_n20#" "and_0/OUT" 3.20833 -cap "a_n940_n20#" "and_0/GND" 9.75595 +cap "a_n940_n20#" "prescaler_0/GND" 3.58696 cap "a_n940_n20#" "and_0/Z1" 5.5 cap "a_n940_n20#" "and_0/out1" 3.20833 -cap "a_n940_n20#" "nor_0/Out" 7 +cap "a_n940_n20#" "and_0/GND" 9.75595 +cap "a_n940_n20#" "and_0/OUT" 3.20833 cap "a_n940_n20#" "and_0/Z1" 0.916667 -cap "a_n940_n20#" "nor_0/GND" 29.5 -cap "a_n940_n20#" "nor_1/GND" 20.3333 +cap "a_n940_n20#" "and_0/GND" 29.5 +cap "a_n940_n20#" "nor_0/Out" 7 cap "a_n940_n20#" "nor_1/Out" 7 +cap "a_n940_n20#" "nor_1/GND" 20.3333 merge "nor_1/GND" "nor_0/gnd!" -270.175 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70100 -2250 0 0 0 0 merge "nor_0/gnd!" "nor_1/gnd!" merge "nor_1/gnd!" "nor_0/GND" @@ -287,9 +287,9 @@ merge "tspc_2/GND" "tspc_1/GND" merge "tspc_1/GND" "tspc_2/gnd!" merge "tspc_2/gnd!" "m4_7020_30#" -merge "m4_7020_30#" "tspc_0/GND" -merge "tspc_0/GND" "prescaler_0/GND" -merge "prescaler_0/GND" "gnd" +merge "m4_7020_30#" "prescaler_0/GND" +merge "prescaler_0/GND" "tspc_0/GND" +merge "tspc_0/GND" "gnd" merge "nor_1/VSUBS" "nor_0/VSUBS" -12309.6 0 0 0 0 0 0 0 0 0 0 331259 -18282 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 935653 -49352 0 0 0 0 0 0 0 0 0 0 0 0 merge "nor_0/VSUBS" "and_0/VSUBS" merge "and_0/VSUBS" "tspc_2/VSUBS" @@ -303,23 +303,23 @@ merge "prescaler_0/m4_2730_1520#" "prescaler_0/nand_1/vdd!" 628.645 0 0 0 0 677908 -39550 0 0 -119000 -1030 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 219820 -1356 -67080 -1036 -67080 -1036 -67080 -1036 -324072 -7758 0 0 0 0 merge "prescaler_0/nand_1/vdd!" "tspc_2/vdd!" merge "tspc_2/vdd!" "m4_7030_1860#" -merge "m4_7030_1860#" "tspc_1/vdd!" -merge "tspc_1/vdd!" "nor_1/vdd!" +merge "m4_7030_1860#" "nor_1/vdd!" merge "nor_1/vdd!" "nor_1/VDD" merge "nor_1/VDD" "nor_0/vdd!" merge "nor_0/vdd!" "nor_0/VDD" -merge "nor_0/VDD" "tspc_0/vdd!" -merge "tspc_0/vdd!" "and_0/vdd!" -merge "and_0/vdd!" "vdd" -merge "vdd" "and_0/VDD" -merge "and_0/VDD" "prescaler_0/tspc_1/vdd!" +merge "nor_0/VDD" "tspc_1/vdd!" +merge "tspc_1/vdd!" "and_0/vdd!" +merge "and_0/vdd!" "and_0/VDD" +merge "and_0/VDD" "tspc_0/vdd!" +merge "tspc_0/vdd!" "vdd" +merge "vdd" "prescaler_0/tspc_1/vdd!" merge "prescaler_0/tspc_1/vdd!" "li_3310_1810#" merge "li_3310_1810#" "prescaler_0/nand_1/VDD" merge "prescaler_0/nand_1/VDD" "tspc_2/w_n140_n70#" merge "tspc_2/w_n140_n70#" "tspc_1/w_n140_n70#" -merge "tspc_1/w_n140_n70#" "tspc_0/w_n140_n70#" -merge "tspc_0/w_n140_n70#" "prescaler_0/tspc_1/w_n140_n70#" -merge "prescaler_0/tspc_1/w_n140_n70#" "prescaler_0/w_1930_2072#" +merge "tspc_1/w_n140_n70#" "prescaler_0/tspc_1/w_n140_n70#" +merge "prescaler_0/tspc_1/w_n140_n70#" "tspc_0/w_n140_n70#" +merge "tspc_0/w_n140_n70#" "prescaler_0/w_1930_2072#" merge "prescaler_0/w_1930_2072#" "w_2780_1920#" merge "nor_1/B" "tspc_2/a_740_n680#" -1006.11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6800 -160 163360 -4720 0 0 0 0 0 0 0 0 0 0 merge "tspc_2/a_740_n680#" "tspc_2/D" @@ -340,8 +340,8 @@ merge "prescaler_0/tspc_2/w_n140_n70#" "prescaler_0/nand_0/vdd!" merge "prescaler_0/nand_0/vdd!" "prescaler_0/nand_0/VDD" merge "prescaler_0/nand_0/VDD" "w_n140_1520#" -merge "tspc_0/a_300_n150#" "prescaler_0/Out" -31.505 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -6600 -140 0 0 0 0 0 0 0 0 -merge "prescaler_0/Out" "m2_3910_680#" +merge "prescaler_0/Out" "tspc_0/a_300_n150#" -31.505 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -6600 -140 0 0 0 0 0 0 0 0 +merge "tspc_0/a_300_n150#" "m2_3910_680#" merge "nor_1/A" "mc2" 128.665 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12000 -80 50800 0 898800 0 0 0 0 0 0 0 0 0 merge "tspc_0/Q" "tspc_1/a_300_n150#" -118.057 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7200 -160 0 0 -45000 -80 0 0 0 0 0 0 0 0 merge "tspc_1/a_300_n150#" "li_5460_820#"
diff --git a/mag/filter.ext b/mag/filter.ext index f85e42a..5223545 100644 --- a/mag/filter.ext +++ b/mag/filter.ext
@@ -16,11 +16,11 @@ node "a_3976_n4798#" 51429 0 3976 -4798 xres 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 126000 3740 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 node "a_3976_n2998#" 382 1341.76 3976 -2998 xpc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120960 4016 151980 1600 0 0 0 0 0 0 0 0 0 0 substrate "v" 0 0 -3380 -20660 ppd 0 0 0 0 0 0 0 0 0 0 4732000 72800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51962080 147668 853254 8326 97600 1760 241185900 76920 35214504 24450 0 0 0 0 -device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -19830 -2459 -19829 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 0 0 -device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -19730 4121 -19729 w=6000 l=6000 "None" "a_3976_n5230#" 22890 0 "v" 0 0 -device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -13520 -2459 -13519 w=6000 l=6000 "None" "a_3976_n5230#" 23680 0 "v" 0 0 -device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -13340 4121 -13339 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 0 0 -device csubckt sky130_fd_pr__cap_mim_m3_1 4770 -7130 4771 -7129 w=6000 l=6000 "None" "v" 22120 0 "v" 0 0 -device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 0 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -19830 -2459 -19829 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 560 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -19730 4121 -19729 w=6000 l=6000 "None" "a_3976_n5230#" 22890 0 "v" 560 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -13520 -2459 -13519 w=6000 l=6000 "None" "a_3976_n5230#" 23680 0 "v" 560 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 4120 -13340 4121 -13339 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 560 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 4770 -7130 4771 -7129 w=6000 l=6000 "None" "v" 22120 0 "v" 560 0 +device csubckt sky130_fd_pr__cap_mim_m3_1 -2460 -7130 -2459 -7129 w=6000 l=6000 "None" "a_3976_n5230#" 22900 0 "v" 560 0 device rsubckt sky130_fd_pr__res_xhigh_po 4294 -4798 4295 -4797 l=1800 w=70 "v" "a_4294_n4798#" 0 0 "v" 70 0 "a_3976_n2998#" 70 0 device rsubckt sky130_fd_pr__res_xhigh_po 3976 -4798 3977 -4797 l=1800 w=70 "v" "a_3976_n4798#" 0 0 "a_3976_n5230#" 70 0 "a_3976_n2998#" 70 0
diff --git a/mag/nand.ext b/mag/nand.ext index 58cede1..6c9c973 100644 --- a/mag/nand.ext +++ b/mag/nand.ext
@@ -1,4 +1,4 @@ -timestamp 1640957762 +timestamp 1640957032 version 8.3 tech sky130A style ngspice() @@ -15,20 +15,20 @@ node "VDD" 1727 1248 -80 -20 nw 0 0 0 0 416000 2580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cap "gnd!" "z1" 159.5 +cap "VDD" "OUT" 2.96 cap "OUT" "z1" 210.754 +cap "VDD" "vdd!" 29.2 cap "OUT" "gnd!" 22 cap "vdd!" "z1" 8.55556 cap "a_280_n230#" "z1" 70.125 cap "vdd!" "gnd!" 8.55556 cap "A" "z1" 8.25 -cap "A" "gnd!" 57.75 cap "vdd!" "OUT" 838.2 +cap "A" "gnd!" 57.75 cap "a_280_n230#" "OUT" 150.608 cap "a_280_n230#" "vdd!" 13.0842 cap "A" "OUT" 9.74286 cap "A" "vdd!" 13.0842 -cap "VDD" "OUT" 2.96 -cap "VDD" "vdd!" 29.2 cap "A" "a_280_n230#" 81.6947 device msubckt sky130_fd_pr__nfet_01v8 310 -450 311 -449 l=30 w=200 "VSUBS" "a_280_n230#" 60 0 "z1" 200 0 "OUT" 200 0 device msubckt sky130_fd_pr__nfet_01v8 60 -450 61 -449 l=30 w=200 "VSUBS" "A" 60 0 "gnd!" 200 0 "z1" 200 0
diff --git a/mag/nor.ext b/mag/nor.ext index 0add68f..709296b 100644 --- a/mag/nor.ext +++ b/mag/nor.ext
@@ -1,4 +1,4 @@ -timestamp 1640957762 +timestamp 1640957264 version 8.3 tech sky130A style ngspice() @@ -14,22 +14,22 @@ node "A" 2231 379.695 -40 -100 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48700 3040 0 0 9200 460 0 0 0 0 0 0 0 0 0 0 0 0 node "VDD" 3542 2250 -110 -30 nw 0 0 0 0 750000 3700 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -cap "Out" "gnd!" 453.75 -cap "Z1" "gnd!" 9.625 -cap "Z1" "Out" 779.396 +cap "Out" "VDD" 2.3125 +cap "B" "Z1" 57.75 cap "vdd!" "gnd!" 9.625 +cap "Z1" "VDD" 2.775 cap "B" "gnd!" 39.7045 -cap "vdd!" "Out" 99 +cap "vdd!" "VDD" 16.2425 +cap "A" "Out" 8.8 cap "A" "gnd!" 19.25 +cap "A" "vdd!" 57.75 +cap "A" "B" 72.9302 +cap "Z1" "Out" 779.396 +cap "gnd!" "Out" 453.75 +cap "gnd!" "Z1" 9.625 +cap "vdd!" "Out" 99 cap "vdd!" "Z1" 749.833 cap "B" "Out" 246.8 -cap "A" "Out" 8.8 -cap "B" "Z1" 57.75 -cap "VDD" "Out" 2.3125 -cap "A" "vdd!" 57.75 -cap "VDD" "Z1" 2.775 -cap "VDD" "vdd!" 16.2425 -cap "A" "B" 72.9302 device msubckt sky130_fd_pr__nfet_01v8 290 -420 291 -419 l=30 w=200 "VSUBS" "B" 60 0 "gnd!" 200 0 "Out" 200 0 device msubckt sky130_fd_pr__nfet_01v8 40 -420 41 -419 l=30 w=200 "VSUBS" "A" 60 0 "gnd!" 200 0 "Out" 200 0 device msubckt sky130_fd_pr__pfet_01v8 290 20 291 21 l=30 w=900 "VDD" "B" 60 0 "Z1" 900 0 "Out" 900 0
diff --git a/mag/pd.ext b/mag/pd.ext index d4e0f1a..3bbc905 100644 --- a/mag/pd.ext +++ b/mag/pd.ext
@@ -4,9 +4,9 @@ style ngspice() scale 1000 1 500000 resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 +use and_pd and_pd_0 1 0 2200 0 1 790 use tspc_r tspc_r_0 1 0 290 0 1 760 use tspc_r tspc_r_1 1 0 290 0 -1 -850 -use and_pd and_pd_0 1 0 2200 0 1 790 node "GND" 1 842.66 20 -130 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 343400 4380 0 0 0 0 node "m4_1440_1280#" 0 173.9 1440 1280 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24600 940 0 0 0 0 node "DIV" 1 109.532 -230 -910 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6900 520 0 0 0 0 0 0 0 0 @@ -19,104 +19,106 @@ node "w_0_n1460#" 18910 2199.75 0 -1460 nw 0 0 0 0 662500 5900 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 45800 1300 0 0 0 0 node "VDD" 27087 2548.65 0 1160 nw 0 0 0 0 793200 7540 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14400 480 14400 480 14400 480 14400 480 37400 1040 0 0 0 0 substrate "a_n420_n1430#" 0 0 -420 -1430 ppd 0 0 0 0 0 0 0 0 0 0 486400 12160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2463100 27820 0 0 0 0 0 0 0 0 0 0 0 0 +cap "w_0_n1460#" "VDD" 0.48 +cap "VDD" "m4_1440_1280#" 4.92 +cap "VDD" "UP" 7.2 cap "R" "GND" 53.75 cap "DOWN" "GND" 50.15 cap "VDD" "GND" 113.9 -cap "VDD" "DIV" 27.9 -cap "VDD" "m4_1440_1280#" 4.92 cap "m1_2010_600#" "UP" 4.5 cap "R" "UP" 72 +cap "VDD" "DIV" 27.9 cap "DOWN" "UP" 101.25 -cap "DOWN" "m1_2010_600#" 41.625 cap "VDD" "REF" 27.9 -cap "DOWN" "R" 185.417 -cap "VDD" "UP" 7.2 cap "VDD" "R" 11.2838 -cap "w_0_n1460#" "VDD" 0.48 cap "VDD" "VDD" 0.48 -cap "tspc_r_0/GND" "tspc_r_1/Z3" 7.21875 +cap "DOWN" "m1_2010_600#" 41.625 +cap "DOWN" "R" 185.417 cap "tspc_r_1/VDD" "tspc_r_1/Z2" 72 cap "tspc_r_1/R" "tspc_r_1/Z3" 11.355 -cap "tspc_r_1/VDD" "tspc_r_0/GND" 99.8267 cap "tspc_r_1/VDD" "tspc_r_1/w_n290_n40#" 33.74 +cap "tspc_r_1/VDD" "tspc_r_0/GND" 99.8267 cap "tspc_r_1/VDD" "tspc_r_1/Z3" 10.9091 cap "tspc_r_1/VDD" "tspc_r_1/R" 100 cap "tspc_r_1/VDD" "tspc_r_1/clk" 62.5 cap "tspc_r_1/w_n290_n40#" "tspc_r_1/Z2" 12.775 cap "tspc_r_0/GND" "tspc_r_1/Z2" 9.69375 cap "tspc_r_0/GND" "tspc_r_1/Z1" 14.4375 -cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 30.4615 +cap "tspc_r_0/GND" "tspc_r_1/Z3" 7.21875 cap "a_n420_n1430#" "tspc_r_1/Qbar" 7.21875 +cap "tspc_r_1/VDD" "tspc_r_1/Qbar" 30.4615 cap "a_n420_n1430#" "tspc_r_1/Q" 7.21875 cap "tspc_r_1/R" "tspc_r_1/Z3" 126.785 cap "a_n420_n1430#" "tspc_r_1/Qbar1" 7.21875 -cap "tspc_r_1/VDD" "tspc_r_1/Qbar1" 5.68434e-14 +cap "tspc_r_1/VDD" "tspc_r_1/Q" -2.37588e-14 +cap "tspc_r_1/VDD" "tspc_r_1/Qbar1" 6.30607e-14 +cap "tspc_r_1/VDD" "tspc_r_1/Z3" 8.88178e-15 cap "tspc_r_1/VDD" "a_n420_n1430#" 45.2812 -cap "tspc_r_0/Z3" "tspc_r_0/R" 13.31 cap "tspc_r_0/VDD" "tspc_r_0/clk" 44.4444 cap "tspc_r_0/GND" "tspc_r_0/VDD" 150.325 cap "tspc_r_0/GND" "tspc_r_1/Z4" 13.3333 +cap "tspc_r_0/Z4" "tspc_r_1/Z4" 19.4595 cap "tspc_r_0/GND" "tspc_r_0/Z4" 13.3333 cap "tspc_r_0/VDD" "tspc_r_0/R" 66.6667 -cap "tspc_r_0/Z4" "tspc_r_1/Z4" 19.4595 cap "tspc_r_0/GND" "tspc_r_0/R" 64.2857 cap "tspc_r_0/VDD" "tspc_r_0/Z2" 72 cap "tspc_r_0/VDD" "tspc_r_0/Z3" 10.9091 -cap "tspc_r_0/GND" "tspc_r_1/z5" 13.3333 -cap "tspc_r_0/GND" "tspc_r_0/R" 145.652 -cap "and_pd_0/Z1" "tspc_r_0/Qbar" 21.0517 -cap "and_pd_0/Z1" "tspc_r_1/Q" 85 -cap "tspc_r_0/GND" "tspc_r_0/Qbar" 44.4044 -cap "tspc_r_0/GND" "tspc_r_0/VDD" 8.88178e-16 -cap "tspc_r_0/GND" "tspc_r_1/Q" 308.57 +cap "tspc_r_0/Z3" "tspc_r_0/R" 13.31 +cap "and_pd_0/GND" "tspc_r_1/z5" 13.3333 +cap "and_pd_0/GND" "tspc_r_0/z5" 13.3333 +cap "tspc_r_0/Qbar" "and_pd_0/Z1" 21.0517 +cap "tspc_r_0/R" "and_pd_0/GND" 145.652 +cap "tspc_r_0/Qbar" "and_pd_0/GND" 44.4044 +cap "and_pd_0/A" "and_pd_0/Z1" 85 cap "tspc_r_0/Qbar" "tspc_r_0/R" 31.025 -cap "tspc_r_0/VDD" "tspc_r_0/Qbar" 68.0625 +cap "and_pd_0/a_n60_n30#" "and_pd_0/GND" 1.77636e-15 +cap "and_pd_0/A" "and_pd_0/GND" 308.57 +cap "and_pd_0/a_n60_n30#" "tspc_r_0/Qbar" 68.0625 +cap "and_pd_0/A" "tspc_r_0/R" 86.5 +cap "and_pd_0/A" "tspc_r_0/Qbar" 17.9186 cap "and_pd_0/Out1" "tspc_r_0/Qbar" 47.6929 -cap "tspc_r_1/Q" "tspc_r_0/R" 86.5 -cap "tspc_r_0/Q" "tspc_r_0/R" 150.845 -cap "tspc_r_1/Q" "tspc_r_0/Qbar" 17.9186 +cap "and_pd_0/B" "tspc_r_0/R" 150.845 cap "tspc_r_0/Qbar1" "tspc_r_0/R" 287.105 cap "tspc_r_0/Z3" "tspc_r_0/R" 143.15 cap "tspc_r_0/clk" "tspc_r_0/R" 103.99 -cap "tspc_r_0/Q" "and_pd_0/Out1" -14.35 -cap "tspc_r_0/Q" "tspc_r_1/Q" 183.938 -cap "tspc_r_0/GND" "tspc_r_0/z5" 13.3333 +cap "and_pd_0/B" "and_pd_0/Out1" -14.35 +cap "and_pd_0/B" "and_pd_0/A" 183.938 cap "tspc_r_0/z5" "tspc_r_1/z5" 19.4595 -cap "tspc_r_0/GND" "a_n420_n1430#" 9.20833 -cap "and_pd_0/Out" "a_n420_n1430#" 72.7883 -cap "and_pd_0/Out" "tspc_r_0/VDD" 56.5714 -cap "tspc_r_1/Q" "and_pd_0/Out1" 105.892 -cap "tspc_r_0/Q" "and_pd_0/Out1" 70.6975 -cap "and_pd_0/Out1" "tspc_r_0/VDD" 12.375 -cap "tspc_r_1/Q" "tspc_r_0/Q" 58.428 -cap "and_pd_0/Out1" "a_n420_n1430#" 6.41667 -cap "tspc_r_0/Q" "tspc_r_0/VDD" 2.66454e-15 -cap "and_pd_0/Z1" "tspc_r_0/Qbar" 1.69231 -cap "and_pd_0/Z1" "tspc_r_1/Q" -23.46 -cap "and_pd_0/Z1" "a_n420_n1430#" 0.916667 -cap "and_pd_0/Out" "tspc_r_0/GND" 16.129 -cap "tspc_r_1/Q" "tspc_r_0/GND" 113.28 +cap "tspc_r_0/Qbar" "and_pd_0/Z1" 1.69231 +cap "and_pd_0/A" "and_pd_0/Z1" -23.46 +cap "a_n420_n1430#" "and_pd_0/Z1" 0.916667 +cap "and_pd_0/Out" "and_pd_0/GND" 16.129 cap "and_pd_0/Out1" "and_pd_0/Out" 137.14 -cap "tspc_r_0/Q" "and_pd_0/Out" 222.129 -cap "tspc_r_1/Q" "and_pd_0/Out" 90.78 -cap "tspc_r_0/w_n290_n40#" "tspc_r_0/Z2" 12.775 -cap "a_n420_n1430#" "tspc_r_0/Z2" 9.69375 -cap "a_n420_n1430#" "tspc_r_0/Z1" 14.4375 -cap "a_n420_n1430#" "tspc_r_0/VDD" 56.7013 -cap "tspc_r_0/w_n290_n40#" "tspc_r_0/VDD" 33.74 +cap "and_pd_0/A" "and_pd_0/GND" 113.28 +cap "and_pd_0/B" "and_pd_0/Out" 222.129 +cap "and_pd_0/A" "and_pd_0/Out" 90.78 +cap "a_n420_n1430#" "and_pd_0/GND" 9.20833 +cap "and_pd_0/VDD" "and_pd_0/Out" 56.5714 +cap "and_pd_0/B" "and_pd_0/Out1" 70.6975 +cap "a_n420_n1430#" "and_pd_0/Out" 72.7883 +cap "and_pd_0/A" "and_pd_0/Out1" 105.892 +cap "a_n420_n1430#" "and_pd_0/Out1" 6.41667 +cap "and_pd_0/VDD" "and_pd_0/B" 2.66454e-15 +cap "and_pd_0/VDD" "and_pd_0/Out1" 12.375 +cap "and_pd_0/A" "and_pd_0/B" 58.428 cap "a_n420_n1430#" "tspc_r_0/Z3" 7.21875 -cap "tspc_r_0/Qbar" "and_pd_0/Out1" 3.53571 -cap "tspc_r_0/VDD" "tspc_r_0/Qbar" 6.1875 +cap "a_n420_n1430#" "tspc_r_0/Z2" 9.69375 +cap "tspc_r_0/w_n290_n40#" "tspc_r_0/Z2" 12.775 +cap "a_n420_n1430#" "tspc_r_0/Z1" 14.4375 +cap "tspc_r_0/w_n290_n40#" "tspc_r_0/VDD" 33.74 +cap "a_n420_n1430#" "tspc_r_0/VDD" 56.7013 +cap "tspc_r_0/Q" "and_pd_0/A" 2.15625 cap "a_n420_n1430#" "and_pd_0/Out1" 7.21875 cap "a_n420_n1430#" "tspc_r_0/Qbar" 7.21875 cap "a_n420_n1430#" "tspc_r_0/Q" 7.21875 cap "a_n420_n1430#" "tspc_r_0/Qbar1" 7.21875 -cap "and_pd_0/VDD" "tspc_r_0/VDD" 43.07 -cap "tspc_r_0/Q" "and_pd_0/A" 2.15625 -cap "a_n420_n1430#" "tspc_r_0/VDD" 54.6607 +cap "and_pd_0/VDD" "and_pd_0/a_n60_n30#" 43.07 +cap "a_n420_n1430#" "and_pd_0/a_n60_n30#" 54.6607 +cap "tspc_r_0/Qbar" "and_pd_0/Out1" 3.53571 +cap "and_pd_0/a_n60_n30#" "tspc_r_0/Qbar" 6.1875 +cap "a_n420_n1430#" "and_pd_0/VDD" 18.7589 cap "a_n420_n1430#" "and_pd_0/Out" 9.96875 cap "a_n420_n1430#" "and_pd_0/Out1" 7.21875 -cap "a_n420_n1430#" "tspc_r_0/VDD" 18.7589 merge "and_pd_0/VSUBS" "and_pd_0/GND" -6351.75 0 0 0 0 0 0 0 0 0 0 -55010 -7926 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 572500 -19033 0 0 0 0 0 0 -601300 -9300 0 0 0 0 merge "and_pd_0/GND" "tspc_r_1/VSUBS" merge "tspc_r_1/VSUBS" "tspc_r_1/GND" @@ -124,13 +126,13 @@ merge "tspc_r_0/VSUBS" "tspc_r_0/GND" merge "tspc_r_0/GND" "GND" merge "GND" "a_n420_n1430#" -merge "and_pd_0/B" "UP" -198.16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -84600 -320 0 0 0 0 0 0 0 0 0 0 -merge "UP" "tspc_r_0/Q" -merge "tspc_r_0/Q" "m1_2010_600#" -merge "and_pd_0/a_n60_n30#" "and_pd_0/VDD" 240.86 0 0 0 0 325700 -10800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3200 -320 32000 0 39000 0 79000 0 83100 -1940 0 0 0 0 -merge "and_pd_0/VDD" "tspc_r_0/VDD" -merge "tspc_r_0/VDD" "m4_1440_1280#" -merge "m4_1440_1280#" "tspc_r_0/D" +merge "tspc_r_0/Q" "and_pd_0/B" -198.16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -84600 -320 0 0 0 0 0 0 0 0 0 0 +merge "and_pd_0/B" "UP" +merge "UP" "m1_2010_600#" +merge "and_pd_0/VDD" "and_pd_0/a_n60_n30#" 240.86 0 0 0 0 325700 -10800 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3200 -320 32000 0 39000 0 79000 0 83100 -1940 0 0 0 0 +merge "and_pd_0/a_n60_n30#" "m4_1440_1280#" +merge "m4_1440_1280#" "tspc_r_0/VDD" +merge "tspc_r_0/VDD" "tspc_r_0/D" merge "tspc_r_0/D" "tspc_r_0/w_n290_n40#" merge "tspc_r_0/w_n290_n40#" "tspc_r_1/VDD" merge "tspc_r_1/VDD" "tspc_r_1/w_n290_n40#"
diff --git a/mag/prescaler.ext b/mag/prescaler.ext index 57d4478..4c762aa 100644 --- a/mag/prescaler.ext +++ b/mag/prescaler.ext
@@ -1,4 +1,4 @@ -timestamp 1640957762 +timestamp 1640957100 version 8.3 tech sky130A style ngspice() @@ -29,36 +29,33 @@ node "w_390_530#" 14707 435.372 390 530 nw 0 0 0 0 145124 2500 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 node "w_1930_2072#" 27928 716.916 1930 2072 nw 0 0 0 0 238972 4204 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -cap "li_n310_330#" "li_3590_420#" 92.2845 -cap "mc1" "m4_2730_1520#" 23.175 -cap "li_n310_330#" "mc1" 37.515 -cap "mc1" "VDD" 41.675 -cap "li_3590_420#" "clk" 168.462 -cap "mc1" "m4_350_1060#" 84.575 -cap "w_1930_2072#" "mc1" 2.7456 cap "li_3590_420#" "m2_970_460#" 183.333 -cap "w_1930_2072#" "li_1980_2130#" 10.7855 +cap "Out" "m1_2700_2190#" 27.465 +cap "w_1930_2072#" "m2_970_460#" 42.9324 cap "li_3590_420#" "m1_2700_2190#" 23.5 cap "li_2030_420#" "m2_970_460#" 17.38 cap "li_450_280#" "clk" 28.72 -cap "GND" "m4_2730_1520#" 23.6471 cap "w_390_530#" "m4_350_1060#" 2.9032 -cap "w_1930_2072#" "VDD" 1.964 cap "li_3590_420#" "Out" 716.418 cap "mc1" "m2_970_460#" 37.515 cap "li_2030_420#" "Out" 197.97 cap "li_n310_330#" "clk" 28.72 cap "mc1" "m1_2700_2190#" 63.2343 cap "li_1980_2130#" "m2_970_460#" 138.025 +cap "w_1930_2072#" "mc1" 2.7456 +cap "w_1930_2072#" "li_1980_2130#" 10.7855 +cap "li_n310_330#" "li_3590_420#" 92.2845 +cap "li_n310_330#" "mc1" 37.515 +cap "GND" "m4_2730_1520#" 23.6471 cap "m2_970_460#" "VDD" 42 -cap "w_1930_2072#" "m2_970_460#" 42.9324 +cap "w_1930_2072#" "VDD" 1.964 cap "Out" "GND" 27.9 -cap "Out" "m1_2700_2190#" 27.465 -cap "nand_0/a_280_n230#" "tspc_0/Z3" 75.9225 -cap "nand_0/a_280_n230#" "tspc_0/Z2" 56.16 -cap "tspc_0/D" "nand_0/z1" 2.11538 -cap "tspc_0/D" "nand_0/A" 29.5549 +cap "mc1" "m4_2730_1520#" 23.175 +cap "mc1" "VDD" 41.675 +cap "li_3590_420#" "clk" 168.462 +cap "mc1" "m4_350_1060#" 84.575 cap "tspc_0/a_300_n150#" "nand_0/A" 17.42 +cap "tspc_0/D" "nand_0/A" 29.5549 cap "nand_0/a_280_n230#" "tspc_0/Z4" 106.442 cap "tspc_0/D" "tspc_0/vdd!" 45.9643 cap "tspc_0/D" "tspc_0/a_300_n150#" 127.12 @@ -69,48 +66,51 @@ cap "nand_0/A" "nand_0/a_280_n230#" 13.02 cap "tspc_0/a_300_n150#" "nand_0/a_280_n230#" 94.1074 cap "tspc_0/D" "nand_0/a_280_n230#" 165.278 -cap "tspc_0/a_740_n680#" "tspc_1/Z2" 5.4 -cap "tspc_0/a_300_n150#" "tspc_0/Q" 177.533 -cap "tspc_0/a_740_n680#" "tspc_0/a_300_n150#" 129.16 -cap "tspc_0/GND" "li_3590_420#" 198.939 -cap "tspc_1/Z4" "li_3590_420#" 55.1 +cap "nand_0/a_280_n230#" "tspc_0/Z3" 75.9225 +cap "nand_0/a_280_n230#" "tspc_0/Z2" 56.16 +cap "tspc_0/D" "nand_0/z1" 2.11538 +cap "tspc_0/a_740_n680#" "tspc_0/Q" 32.1861 cap "tspc_0/Q" "li_3590_420#" 142.71 +cap "tspc_0/Q" "tspc_1/Z3" 3.50402 +cap "tspc_0/Z3" "li_3590_420#" 57.62 +cap "tspc_0/a_300_n150#" "li_3590_420#" 83.0378 +cap "tspc_0/a_740_n680#" "tspc_0/a_300_n150#" 129.16 cap "tspc_0/a_740_n680#" "li_3590_420#" 150.46 -cap "tspc_0/a_300_n150#" "tspc_0/Z3" 198.42 -cap "tspc_0/a_630_n680#" "tspc_0/GND" 17.3347 -cap "tspc_0/Z4" "li_3590_420#" 107.677 +cap "tspc_0/GND" "tspc_0/a_630_n680#" 17.3347 +cap "tspc_1/Z2" "tspc_0/GND" 16.9342 +cap "tspc_0/Q" "tspc_1/Z4" 102.17 cap "tspc_0/Q" "tspc_0/GND" 51.0882 -cap "tspc_1/Z2" "li_3590_420#" 43.32 -cap "tspc_1/Z3" "tspc_0/Q" 3.50402 -cap "tspc_1/Z4" "tspc_0/Q" 102.17 +cap "tspc_0/Q" "tspc_1/Z2" 85.89 cap "tspc_0/Q" "tspc_1/Z1" 39.5832 cap "tspc_0/Q" "tspc_1/vdd!" 59.1194 -cap "tspc_1/Z4" "tspc_0/a_740_n680#" 4.09091 +cap "tspc_0/a_740_n680#" "tspc_1/Z4" 4.09091 +cap "tspc_1/Z4" "li_3590_420#" 55.1 +cap "tspc_0/a_300_n150#" "tspc_0/Q" 177.533 +cap "tspc_0/GND" "li_3590_420#" 198.939 cap "tspc_0/vdd!" "tspc_1/vdd!" 38.2105 -cap "tspc_0/Z3" "li_3590_420#" 57.62 -cap "tspc_0/a_740_n680#" "tspc_0/Q" 32.1861 -cap "tspc_0/a_300_n150#" "li_3590_420#" 83.0378 -cap "tspc_1/Z2" "tspc_0/GND" 16.9342 -cap "tspc_0/Q" "tspc_1/Z2" 85.89 -cap "tspc_1/Q" "tspc_1/Z4" 104.585 -cap "tspc_0/Q" "tspc_1/a_300_n150#" 179.587 -cap "tspc_1/a_740_n680#" "tspc_0/Q" 82.65 -cap "tspc_0/Q" "tspc_1/GND" 39.1 -cap "tspc_1/Z3" "tspc_1/Q" 156.507 +cap "tspc_0/a_300_n150#" "tspc_0/Z3" 198.42 +cap "tspc_0/Z4" "li_3590_420#" 107.677 +cap "tspc_1/Z2" "li_3590_420#" 43.32 +cap "tspc_0/a_740_n680#" "tspc_1/Z2" 5.4 cap "tspc_1/Z2" "tspc_1/Q" 12.84 cap "tspc_1/Z4" "tspc_0/a_740_n680#" 1.92857 +cap "tspc_0/Q" "tspc_1/Q" 50.6 cap "tspc_0/Q" "tspc_1/Z4" 78.2567 cap "tspc_1/a_300_n150#" "tspc_1/Q" 68.7785 -cap "tspc_0/Q" "tspc_1/Q" 50.6 cap "tspc_1/a_740_n680#" "tspc_1/Q" 175.043 -cap "tspc_1/Q" "tspc_1/GND" 218.86 cap "tspc_0/Q" "tspc_1/Z3" 59.529 cap "tspc_0/Q" "tspc_1/Z2" 9.99 +cap "tspc_0/Q" "tspc_1/a_300_n150#" 179.587 +cap "tspc_1/a_740_n680#" "tspc_0/Q" 82.65 +cap "tspc_1/Q" "tspc_1/GND" 218.86 +cap "tspc_0/Q" "tspc_1/GND" 39.1 +cap "tspc_1/Q" "tspc_1/Z4" 104.585 +cap "tspc_1/Z3" "tspc_1/Q" 156.507 cap "tspc_0/vdd!" "mc1" 162.542 cap "tspc_0/vdd!" "tspc_0/Z2" 10 -cap "tspc_0/Z2" "mc1" 46.8 cap "tspc_2/Q" "tspc_0/vdd!" 32.5248 cap "tspc_0/w_n140_n70#" "tspc_0/vdd!" -3.656 +cap "tspc_0/Z2" "mc1" 46.8 cap "tspc_0/w_n140_n70#" "mc1" 9.165 cap "tspc_0/Z2" "mc1" 17.4522 cap "tspc_0/vdd!" "tspc_2/Z2" 10 @@ -131,25 +131,25 @@ cap "tspc_0/vdd!" "tspc_1/Z2" 4.35484 cap "tspc_2/w_n140_n70#" "mc1" 24.5544 cap "tspc_0/Q" "tspc_1/Z1" 10.4211 -cap "nand_1/A" "tspc_1/vdd!" 227.695 -cap "nand_1/a_280_n230#" "tspc_1/vdd!" 13.125 -cap "tspc_2/w_n140_n70#" "tspc_1/vdd!" -6.44 -cap "nand_1/a_280_n230#" "tspc_1/a_740_n680#" 1.36364 -cap "nand_1/A" "tspc_1/Z2" 46.2522 +cap "tspc_1/Z2" "nand_1/A" 46.2522 +cap "tspc_1/vdd!" "nand_1/A" 227.695 +cap "tspc_1/vdd!" "nand_1/a_280_n230#" 13.125 +cap "tspc_1/vdd!" "tspc_2/w_n140_n70#" -6.44 +cap "tspc_1/vdd!" "tspc_2/a_300_n150#" 1.38889 cap "nand_1/OUT" "nand_1/z1" 1.83333 cap "nand_1/A" "nand_1/OUT" 22.3793 cap "tspc_2/w_n140_n70#" "nand_1/A" 9.555 -cap "nand_1/GND" "tspc_1/vdd!" 39.5155 -cap "tspc_1/vdd!" "tspc_2/a_300_n150#" 1.38889 cap "tspc_1/vdd!" "tspc_1/Z2" 11.9132 +cap "tspc_1/a_740_n680#" "nand_1/a_280_n230#" 1.36364 +cap "nand_1/GND" "tspc_1/vdd!" 39.5155 cap "tspc_2/Q" "tspc_2/a_740_n680#" 18.4737 -cap "tspc_2/D" "tspc_2/Z4" 7.71692 -cap "tspc_2/a_300_n150#" "tspc_2/D" 0.18 -cap "tspc_2/Z3" "tspc_2/D" 5.25747 -cap "tspc_2/w_n140_n70#" "tspc_2/D" 3.0525 cap "nand_1/z1" "tspc_2/D" 14 cap "tspc_2/vdd!" "tspc_2/D" 47.4 cap "tspc_2/Z1" "tspc_2/D" 20.5588 +cap "tspc_2/D" "tspc_2/a_300_n150#" 0.18 +cap "tspc_2/D" "tspc_2/Z3" 5.25747 +cap "tspc_2/D" "tspc_2/w_n140_n70#" 3.0525 +cap "tspc_2/Z4" "tspc_2/D" 7.71692 cap "nand_1/OUT" "nand_1/z1" 2.75 merge "tspc_2/gnd!" "tspc_2/GND" -681.99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -218700 -3450 0 0 0 0 merge "tspc_2/GND" "nand_1/GND"
diff --git a/mag/ro_complete.ext b/mag/ro_complete.ext index e004783..699ee8a 100644 --- a/mag/ro_complete.ext +++ b/mag/ro_complete.ext
@@ -1,13 +1,13 @@ -timestamp 1640956319 +timestamp 1640959832 version 8.3 tech sky130A style ngspice() scale 1000 1 500000 resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 -use ro_var_extend ro_var_extend_0 1 0 974 0 1 1350 use cbank cbank_1 1 0 -84 0 1 -5410 use cbank cbank_2 1 0 -84 0 1 -8980 use cbank cbank_0 1 0 -84 0 1 -1870 +use ro_var_extend ro_var_extend_0 1 0 974 0 1 1350 node "a5" 1492 5300.76 6856 -8790 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 599200 17260 0 0 0 0 0 0 0 0 0 0 0 0 node "a4" 1403 4987.24 5834 -8790 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 563500 16240 0 0 0 0 0 0 0 0 0 0 0 0 node "a3" 1403 4987.24 4852 -8790 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 563500 16240 0 0 0 0 0 0 0 0 0 0 0 0 @@ -18,122 +18,122 @@ node "li_1010_1400#" 88 1456.19 1010 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38800 1200 19600 560 19600 560 19600 560 196600 4100 0 0 0 0 node "li_7140_1400#" 85 6989.63 7140 1400 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50400 1320 32400 720 2607360 22208 57600 960 57600 960 0 0 0 0 substrate "a_7790_n10640#" 0 0 7790 -10640 ppd 0 0 0 0 0 0 0 0 0 0 1216800 18720 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1036800 17280 1349800 21100 1085200 18160 1085200 18160 3951000 27540 0 0 0 0 -cap "li_4080_1390#" "a5" 77.72 -cap "li_7140_1400#" "a5" 100.96 +cap "a5" "li_4080_1390#" 77.72 +cap "a5" "li_7140_1400#" 100.96 cap "cbank_2/a0" "cbank_2/switch_0/vout" 46.5385 -cap "cbank_2/a1" "cbank_2/switch_1/vout" 46.5385 cap "cbank_2/a2" "cbank_2/switch_2/vout" 46.5385 -cap "cbank_2/a3" "cbank_2/switch_3/vout" 46.5385 +cap "cbank_2/a1" "cbank_2/switch_1/vout" 46.5385 +cap "cbank_2/switch_3/vout" "cbank_2/a3" 46.5385 cap "cbank_2/a5" "cbank_2/switch_5/vout" 12.6923 cap "cbank_2/a4" "cbank_2/switch_4/vout" 46.5385 cap "li_7140_1400#" "cbank_2/switch_5/vin" 24 cap "cbank_2/switch_5/vout" "cbank_2/a5" 33.8462 -cap "cbank_2/v" "cbank_1/gnd!" 86.7059 +cap "cbank_1/gnd!" "cbank_2/v" 86.7059 cap "cbank_1/switch_1/vin" "a0" 21.8167 -cap "cbank_1/switch_0/vout" "a0" 181.38 -cap "a0" "cbank_2/v" 53.41 -cap "cbank_1/switch_0/vout" "cbank_2/v" 275.882 -cap "a1" "cbank_2/v" 53.41 -cap "cbank_1/switch_1/vout" "cbank_2/v" 275.882 -cap "cbank_1/switch_2/vin" "a1" 23.6566 -cap "cbank_1/switch_1/vout" "a1" 209.96 -cap "cbank_1/switch_1/vout" "a2" 60.0024 cap "cbank_1/gnd!" "cbank_2/v" 275.882 +cap "cbank_1/gnd!" "a0" 181.38 +cap "a0" "cbank_2/v" 53.41 +cap "cbank_2/v" "cbank_1/switch_1/vout" 275.882 +cap "a2" "cbank_1/switch_1/vout" 60.0024 +cap "a1" "cbank_1/switch_1/vout" 209.96 +cap "a1" "cbank_2/v" 53.41 +cap "cbank_1/switch_2/vin" "a1" 23.6566 +cap "cbank_1/switch_4/vin" "a3" 11.4157 +cap "cbank_1/gnd!" "cbank_2/v" 275.882 +cap "cbank_1/switch_3/vin" "a2" 23.515 cap "cbank_1/gnd!" "a3" 192.323 cap "cbank_1/gnd!" "a2" 124.302 -cap "cbank_1/switch_4/vin" "a3" 11.4157 cap "a3" "cbank_2/v" 53.41 cap "a2" "cbank_2/v" 53.41 -cap "cbank_1/switch_3/vin" "a2" 23.515 -cap "a3" "cbank_1/switch_4/vin" 11.4157 cap "a4" "li_7140_1400#" 53.41 cap "cbank_1/switch_4/vout" "li_7140_1400#" 275.882 cap "cbank_1/switch_5/vin" "a4" 20.5602 cap "cbank_1/switch_4/vout" "a4" 190.632 -cap "a_7790_n10640#" "cbank_1/switch_5/vout" 162.097 -cap "li_7140_1400#" "cbank_1/switch_5/vout" 233.936 -cap "a5" "cbank_1/switch_5/vout" 124.931 +cap "cbank_1/switch_4/vin" "a3" 11.4157 +cap "cbank_1/switch_5/vout" "a_7790_n10640#" 162.097 cap "li_7140_1400#" "cbank_2/a_6660_n30#" 126 +cap "cbank_1/switch_5/vout" "li_7140_1400#" 233.936 +cap "cbank_1/switch_5/vout" "a5" 124.931 cap "cbank_1/gnd!" "a_7790_n10640#" 45.6818 -cap "cbank_1/switch_1/vin" "cbank_1/a0" 106.517 -cap "cbank_1/switch_0/vout" "cbank_1/a0" 248.36 +cap "cbank_1/a0" "cbank_1/switch_1/vin" 106.517 +cap "cbank_1/a0" "cbank_1/switch_0/vout" 248.36 cap "cbank_1/a2" "cbank_1/switch_1/vout" 149.619 cap "cbank_1/a1" "cbank_1/switch_2/vin" 115.5 cap "cbank_1/a1" "cbank_1/switch_1/vout" 289.235 -cap "cbank_1/a3" "cbank_1/gnd!" 264.413 -cap "cbank_1/a2" "cbank_1/gnd!" 103.081 cap "cbank_1/a3" "cbank_1/switch_4/vin" 55.7355 cap "cbank_1/a2" "cbank_1/switch_3/vin" 114.808 -cap "cbank_1/switch_5/vin" "cbank_1/a4" 100.382 -cap "cbank_1/switch_4/vout" "cbank_1/a4" 261.965 +cap "cbank_1/gnd!" "cbank_1/a3" 264.413 +cap "cbank_1/gnd!" "cbank_1/a2" 103.081 cap "cbank_1/switch_4/vin" "a3" 55.7355 cap "cbank_1/a5" "cbank_1/switch_4/vout" 12.6923 +cap "cbank_1/a4" "cbank_1/switch_5/vin" 100.382 +cap "cbank_1/a4" "cbank_1/switch_4/vout" 261.965 cap "cbank_1/a5" "cbank_1/switch_5/vout" 143.406 -cap "cbank_1/v" "cbank_0/gnd!" 47.5484 +cap "cbank_0/gnd!" "cbank_1/v" 47.5484 cap "cbank_0/gnd!" "cbank_1/v" 151.29 cap "cbank_1/a0" "cbank_1/v" 53.41 cap "cbank_1/v" "cbank_1/a1" 53.41 cap "cbank_0/gnd!" "cbank_1/v" 151.29 +cap "cbank_1/v" "cbank_0/gnd!" 151.29 cap "cbank_1/v" "cbank_1/a3" 53.41 cap "cbank_1/v" "cbank_1/a2" 53.41 -cap "cbank_1/v" "cbank_0/gnd!" 151.29 -cap "li_4080_1390#" "cbank_0/gnd!" 151.29 -cap "li_4080_1390#" "cbank_1/a4" 53.41 +cap "cbank_0/gnd!" "li_4080_1390#" 151.29 +cap "cbank_1/a4" "li_4080_1390#" 53.41 cap "cbank_0/gnd!" "li_4080_1390#" 41.6979 -cap "li_4080_1390#" "cbank_1/switch_5/vin" 133.875 -cap "cbank_1/v" "cbank_0/gnd!" 47.5484 -cap "cbank_0/switch_0/vout" "cbank_1/v" 151.29 +cap "cbank_1/switch_5/vin" "li_4080_1390#" 133.875 +cap "cbank_0/gnd!" "cbank_1/v" 47.5484 cap "cbank_0/switch_1/vin" "a0" 82.3167 -cap "cbank_0/switch_0/vout" "a0" 296.011 +cap "cbank_1/v" "cbank_0/gnd!" 151.29 +cap "a0" "cbank_0/gnd!" 296.011 cap "cbank_0/switch_1/vout" "cbank_1/v" 151.29 cap "cbank_0/switch_1/vout" "a2" 118.551 cap "cbank_0/switch_2/vin" "a1" 89.259 cap "cbank_0/switch_1/vout" "a1" 347.808 -cap "cbank_0/gnd!" "a2" 182.851 cap "cbank_0/switch_4/vin" "a3" 43.0727 cap "cbank_0/switch_3/vin" "a2" 88.7246 cap "cbank_0/gnd!" "cbank_1/v" 151.29 cap "cbank_0/gnd!" "a3" 316.073 -cap "cbank_0/switch_4/vin" "a3" 43.0727 +cap "cbank_0/gnd!" "a2" 182.851 cap "cbank_0/switch_4/vout" "li_4080_1390#" 151.29 -cap "cbank_0/switch_4/vout" "a4" 312.991 cap "cbank_0/switch_5/vin" "a4" 77.5759 -cap "a_7790_n10640#" "cbank_0/switch_5/vout" 193.269 +cap "cbank_0/switch_4/vout" "a4" 312.991 +cap "cbank_0/switch_4/vin" "a3" 43.0727 +cap "cbank_0/switch_5/vout" "a5" 187.16 +cap "cbank_0/switch_5/vout" "a_7790_n10640#" 193.269 cap "cbank_0/switch_5/vout" "li_4080_1390#" 438.698 cap "cbank_0/switch_5/vout" "li_7140_1400#" 142.26 -cap "cbank_0/switch_5/vout" "a5" 187.16 cap "cbank_0/gnd!" "a_7790_n10640#" 45.6818 -cap "cbank_0/switch_1/vin" "cbank_0/a0" 46.0167 -cap "cbank_0/switch_0/vout" "cbank_0/a0" 133.728 +cap "cbank_0/a0" "cbank_0/switch_1/vin" 46.0167 +cap "cbank_0/a0" "cbank_0/switch_0/vout" 133.728 cap "cbank_0/a2" "cbank_0/switch_2/vout" 91.0707 cap "cbank_0/a1" "cbank_0/switch_2/vin" 49.8976 cap "cbank_0/a1" "cbank_0/switch_1/vout" 151.387 -cap "cbank_0/a2" "cbank_0/switch_3/vin" 49.5988 -cap "cbank_0/a2" "cbank_0/switch_2/vout" 44.5323 -cap "cbank_0/switch_4/vin" "cbank_0/a3" 24.0785 cap "cbank_0/switch_3/vout" "cbank_0/a3" 140.663 -cap "cbank_0/switch_5/vout" "cbank_0/a5" 12.6923 -cap "cbank_0/switch_5/vin" "cbank_0/a4" 43.3665 -cap "cbank_0/switch_4/vout" "cbank_0/a4" 139.606 +cap "cbank_0/switch_4/vin" "cbank_0/a3" 24.0785 +cap "cbank_0/switch_3/vin" "cbank_0/a2" 49.5988 +cap "cbank_0/switch_2/vout" "cbank_0/a2" 44.5323 cap "cbank_0/switch_4/vin" "a3" 24.0785 +cap "cbank_0/a5" "cbank_0/switch_5/vout" 12.6923 +cap "cbank_0/a4" "cbank_0/switch_5/vin" 43.3665 +cap "cbank_0/a4" "cbank_0/switch_4/vout" 139.606 cap "cbank_0/a5" "cbank_0/switch_5/vout" 81.1776 -cap "cbank_0/v" "ro_var_extend_0/gnd" 151.9 -cap "ro_var_extend_0/gnd" "li_4080_1390#" 796.97 -cap "li_4080_1390#" "ro_var_extend_0/gnd" 769.58 -cap "li_4080_1390#" "ro_var_extend_0/w_n120_n750#" 415.935 -cap "li_7140_1400#" "ro_var_extend_0/w_n120_n750#" 294.59 +cap "ro_var_extend_0/gnd" "cbank_0/v" 151.9 +cap "li_4080_1390#" "ro_var_extend_0/gnd" 796.97 +cap "ro_var_extend_0/gnd" "li_4080_1390#" 769.58 +cap "ro_var_extend_0/w_n120_n750#" "li_4080_1390#" 415.935 +cap "ro_var_extend_0/w_n120_n750#" "li_7140_1400#" 294.59 cap "ro_var_extend_0/out1" "ro_var_extend_0/gnd" 69.0462 -cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703 -cap "ro_var_extend_0/out1" "ro_var_extend_0/w_n120_n750#" 100.15 cap "ro_var_extend_0/out1" "ro_var_extend_0/out3" 116.667 cap "ro_var_extend_0/out1" "ro_var_extend_0/out1" 120.023 -cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out2" 184.5 +cap "ro_var_extend_0/gnd" "ro_var_extend_0/out1" 129.703 +cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/out1" 100.15 +cap "ro_var_extend_0/out2" "ro_var_extend_0/gnd" 259.55 +cap "ro_var_extend_0/out2" "ro_var_extend_0/w_n120_n750#" 184.5 cap "ro_var_extend_0/out2" "ro_var_extend_0/out3" 100 cap "ro_var_extend_0/out2" "ro_var_extend_0/out2" 113.031 -cap "ro_var_extend_0/gnd" "ro_var_extend_0/out2" 259.55 -cap "ro_var_extend_0/vcont" "ro_var_extend_0/w_n120_n750#" 214.76 -cap "ro_var_extend_0/vcont" "ro_var_extend_0/gnd" -11.167 -cap "ro_var_extend_0/out3" "ro_var_extend_0/gnd" 392.251 +cap "ro_var_extend_0/w_n120_n750#" "ro_var_extend_0/vcont" 214.76 +cap "ro_var_extend_0/gnd" "ro_var_extend_0/vcont" -11.167 +cap "ro_var_extend_0/gnd" "ro_var_extend_0/out3" 392.251 merge "cbank_0/a4" "cbank_1/a4" -1801.69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -154480 -6032 0 0 0 0 0 0 0 0 0 0 0 0 merge "cbank_1/a4" "cbank_2/a4" merge "cbank_2/a4" "a4"
diff --git a/mag/ro_complete.mag b/mag/ro_complete.mag index a213b17..a28fa21 100644 --- a/mag/ro_complete.mag +++ b/mag/ro_complete.mag
@@ -1,10 +1,6 @@ magic tech sky130A -timestamp 1640956319 -<< error_s >> -rect 808 -1589 898 -1180 -rect 808 -3359 898 -2639 -rect 808 -5144 898 -4424 +timestamp 1640959700 << psubdiff >> rect 4315 75 4445 90 rect 4315 -25 4330 75 @@ -667,22 +663,22 @@ rect 4095 -5305 4330 -5205 rect 4430 -5305 4455 -5205 rect 4095 -5330 4455 -5305 -use ro_var_extend ro_var_extend_0 -timestamp 1640956303 -transform 1 0 487 0 1 675 -box -375 -595 3780 765 use cbank cbank_1 -timestamp 1640901595 +timestamp 1640959700 transform 1 0 -42 0 1 -2705 box -15 -840 4075 775 use cbank cbank_2 -timestamp 1640901595 +timestamp 1640959700 transform 1 0 -42 0 1 -4490 box -15 -840 4075 775 use cbank cbank_0 -timestamp 1640901595 +timestamp 1640959700 transform 1 0 -42 0 1 -935 box -15 -840 4075 775 +use ro_var_extend ro_var_extend_0 +timestamp 1640959680 +transform 1 0 487 0 1 675 +box -375 -595 3780 765 << labels >> rlabel locali 1123 -825 1123 -825 1 a0 rlabel locali 1617 -830 1617 -830 1 a1
diff --git a/mag/ro_var_extend.ext b/mag/ro_var_extend.ext index 4a57b02..de1eaa2 100644 --- a/mag/ro_var_extend.ext +++ b/mag/ro_var_extend.ext
@@ -1,4 +1,4 @@ -timestamp 1640956303 +timestamp 1640959680 version 8.3 tech sky130A style ngspice() @@ -12,18 +12,18 @@ node "out1" 2948 5653.45 -50 -20 ndif 0 0 0 0 0 0 0 0 20000 600 40000 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70084 2720 0 0 240084 7768 367400 7548 0 0 0 0 0 0 0 0 0 0 node "out3" 2411 3990.47 -190 220 p 0 0 0 0 0 0 0 0 20000 600 40000 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 70084 2720 0 0 76164 2368 111640 2644 647000 13140 0 0 0 0 0 0 0 0 node "w_n120_n750#" 20671 4346.02 -120 -750 nw 0 0 0 0 363304 4204 0 0 116400 3564 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37536 2616 1153264 13180 0 0 0 0 0 0 0 0 0 0 -node "vdd" 20170 18367.8 -250 320 nw 0 0 0 0 4464300 14320 0 0 35200 860 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0 +node "vdd" 21463 18367.8 -250 320 nw 0 0 0 0 4464300 14320 0 0 105600 2580 120000 3000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1276520 16068 0 0 0 0 0 0 0 0 0 0 0 0 substrate "gnd" 0 0 -710 -890 ppd 0 0 0 0 0 0 0 0 60000 1800 1604600 26100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7902720 57188 0 0 0 0 0 0 0 0 0 0 0 0 +cap "out1" "out2" 40.8506 +cap "w_n120_n750#" "vcont" 140.194 cap "out3" "out2" 1263.05 cap "w_n120_n750#" "out2" 789.263 cap "out3" "out1" 1156.32 cap "w_n120_n750#" "out1" 569.035 cap "vdd" "out2" 235.622 -cap "vdd" "out1" 230.66 cap "w_n120_n750#" "out3" 215.464 +cap "vdd" "out1" 230.66 cap "vdd" "out3" 230.554 -cap "w_n120_n750#" "vcont" 140.194 -cap "out1" "out2" 40.8506 device subckt sky130_fd_pr__cap_var_lvt 5955 -694 5956 -693 l=36 w=200 "w_n120_n750#" "out3" 72 0 "w_n120_n750#" 400 0 device subckt sky130_fd_pr__cap_var_lvt 2991 -690 2992 -689 l=36 w=200 "w_n120_n750#" "out2" 72 0 "w_n120_n750#" 400 0 device subckt sky130_fd_pr__cap_var_lvt 17 -688 18 -687 l=36 w=200 "w_n120_n750#" "out1" 72 0 "w_n120_n750#" 400 0
diff --git a/mag/ro_var_extend.mag b/mag/ro_var_extend.mag index 4afb2cd..3e91bed 100644 --- a/mag/ro_var_extend.mag +++ b/mag/ro_var_extend.mag
@@ -1,7 +1,7 @@ magic tech sky130A magscale 1 2 -timestamp 1640956303 +timestamp 1640959680 << nwell >> rect -250 320 6220 1010 rect -120 -750 190 -360 @@ -290,10 +290,18 @@ rect 6770 -1120 6800 -920 rect 6540 -1150 6800 -1120 << nsubdiff >> +rect 174 950 494 970 +rect 174 880 204 950 +rect 464 880 494 950 +rect 174 860 494 880 rect 2834 950 3154 970 rect 2834 880 2864 950 rect 3124 880 3154 950 rect 2834 860 3154 880 +rect 5244 950 5564 970 +rect 5244 880 5274 950 +rect 5534 880 5564 950 +rect 5244 860 5564 880 rect -80 -512 17 -488 rect -80 -664 -68 -512 rect -34 -664 17 -512 @@ -347,7 +355,9 @@ rect 5590 -1120 5790 -920 rect 6570 -1120 6770 -920 << nsubdiffcont >> +rect 204 880 464 950 rect 2864 880 3124 950 +rect 5274 880 5534 950 rect -68 -664 -34 -512 rect 104 -664 138 -512 rect 2906 -666 2940 -514 @@ -424,8 +434,10 @@ rect 7230 1100 7300 1200 rect 7500 1100 7560 1300 rect -250 950 6220 1010 -rect -250 880 2864 950 -rect 3124 880 6220 950 +rect -250 880 204 950 +rect 464 880 2864 950 +rect 3124 880 5274 950 +rect 5534 880 6220 950 rect -250 830 6220 880 rect -200 730 -120 830 rect 2874 750 2954 830
diff --git a/mag/switch.ext b/mag/switch.ext index b5399a5..fadf98e 100644 --- a/mag/switch.ext +++ b/mag/switch.ext
@@ -9,7 +9,7 @@ node "vin" 1082 0 -190 0 ndif 0 0 0 0 0 0 0 0 259200 3240 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196000 3080 0 0 0 0 0 0 0 0 0 0 0 0 node "vcont" 1139 384.82 -40 1460 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124600 3560 0 0 19600 560 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "vin" "vout" 420 cap "vcont" "vout" 16.5 cap "vcont" "vin" 8.25 -cap "vin" "vout" 420 device msubckt sky130_fd_pr__nfet_01v8 -10 0 -9 1 l=70 w=1440 "VSUBS" "vcont" 140 0 "vin" 1440 0 "vout" 1440 0
diff --git a/mag/tspc.ext b/mag/tspc.ext index 2f7fa47..9b3f9ec 100644 --- a/mag/tspc.ext +++ b/mag/tspc.ext
@@ -1,4 +1,4 @@ -timestamp 1640957762 +timestamp 1640956963 version 8.3 tech sky130A style ngspice() @@ -19,54 +19,54 @@ node "a_740_n680#" 3851 1353.54 740 -680 ndif 0 0 0 0 0 0 0 0 16000 560 24000 760 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53200 3440 0 0 51300 2040 67500 3960 0 0 0 0 0 0 0 0 0 0 node "w_n140_n70#" 2516 4440 -140 -70 nw 0 0 0 0 1480000 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -cap "Z2" "Z3" 161.5 -cap "Z1" "Z3" 62.0085 -cap "Z1" "Z2" 1068.12 -cap "a_300_n150#" "Z3" 446.312 -cap "D" "Z3" 46.1286 -cap "a_300_n150#" "Z2" 110.226 +cap "Q" "w_n140_n70#" 6.845 +cap "Z1" "w_n140_n70#" 4.1625 +cap "vdd!" "a_300_n150#" 20.3736 cap "vdd!" "Z3" 671.367 cap "D" "Z2" 91.0218 -cap "D" "Z1" 26.4 +cap "a_300_n150#" "w_n140_n70#" 0.665 +cap "Z3" "w_n140_n70#" 2.3125 cap "vdd!" "Z2" 359.159 -cap "a_740_n680#" "Z3" 334.495 -cap "vdd!" "Z1" 583.229 -cap "w_n140_n70#" "Z3" 2.3125 -cap "D" "a_300_n150#" 132.679 -cap "vdd!" "a_300_n150#" 20.3736 -cap "w_n140_n70#" "Z2" 14.44 -cap "a_740_n680#" "a_300_n150#" 12.4103 +cap "Z2" "w_n140_n70#" 14.44 cap "vdd!" "D" 19.4229 -cap "w_n140_n70#" "Z1" 4.1625 -cap "w_n140_n70#" "a_300_n150#" 0.665 +cap "vdd!" "w_n140_n70#" 85.4425 +cap "a_740_n680#" "a_630_n680#" 190.867 +cap "a_740_n680#" "gnd!" 224.895 +cap "a_740_n680#" "Z4" 82.0167 +cap "Q" "a_630_n680#" 36.6667 +cap "a_300_n150#" "a_630_n680#" 9.625 cap "Z3" "a_630_n680#" 54.2903 +cap "Q" "gnd!" 289.808 cap "Z2" "a_630_n680#" 6.6 cap "Z3" "gnd!" 265.176 -cap "a_740_n680#" "vdd!" 515.003 -cap "Z3" "Z4" 651.52 -cap "Z2" "gnd!" 156.712 -cap "w_n140_n70#" "vdd!" 85.4425 -cap "Z2" "Z4" 361.112 -cap "a_300_n150#" "a_630_n680#" 9.625 -cap "Z3" "Q" 52.8649 -cap "w_n140_n70#" "a_740_n680#" 18.5775 cap "a_300_n150#" "gnd!" 22.7597 cap "Z1" "Z4" 3.38462 -cap "D" "gnd!" 27.9314 cap "a_300_n150#" "Z4" 118.945 -cap "a_740_n680#" "a_630_n680#" 190.867 +cap "Z3" "Z4" 651.52 +cap "Z2" "gnd!" 156.712 +cap "Z2" "Z4" 361.112 +cap "D" "gnd!" 27.9314 cap "D" "Z4" 97.7372 -cap "a_740_n680#" "gnd!" 224.895 cap "vdd!" "Z4" 7.7 -cap "a_740_n680#" "Z4" 82.0167 -cap "vdd!" "Q" 607.82 cap "a_740_n680#" "Q" 178.823 -cap "w_n140_n70#" "Q" 6.845 +cap "a_740_n680#" "a_300_n150#" 12.4103 +cap "a_740_n680#" "Z3" 334.495 +cap "a_740_n680#" "vdd!" 515.003 +cap "a_740_n680#" "w_n140_n70#" 18.5775 cap "gnd!" "a_630_n680#" 610.469 +cap "Z3" "Q" 52.8649 +cap "Z3" "Z1" 62.0085 cap "Z4" "a_630_n680#" 121.707 -cap "Q" "a_630_n680#" 36.6667 +cap "Z2" "Z1" 1068.12 +cap "Z3" "a_300_n150#" 446.312 cap "Z4" "gnd!" 441.644 -cap "Q" "gnd!" 289.808 +cap "Z2" "Z3" 161.5 +cap "Z2" "a_300_n150#" 110.226 +cap "D" "Z1" 26.4 +cap "D" "Z3" 46.1286 +cap "vdd!" "Z1" 583.229 +cap "vdd!" "Q" 607.82 +cap "D" "a_300_n150#" 132.679 device msubckt sky130_fd_pr__nfet_01v8 1210 -680 1211 -679 l=30 w=400 "VSUBS" "a_740_n680#" 60 0 "gnd!" 400 0 "Q" 400 0 device msubckt sky130_fd_pr__nfet_01v8 960 -680 961 -679 l=30 w=200 "VSUBS" "Z3" 60 0 "gnd!" 200 0 "a_630_n680#" 200 0 device msubckt sky130_fd_pr__nfet_01v8 710 -680 711 -679 l=30 w=200 "VSUBS" "a_300_n150#" 60 0 "a_630_n680#" 200 0 "a_740_n680#" 200 0
diff --git a/mag/tspc_r.ext b/mag/tspc_r.ext index b127324..44bd29b 100644 --- a/mag/tspc_r.ext +++ b/mag/tspc_r.ext
@@ -1,4 +1,4 @@ -timestamp 1640958486 +timestamp 1640770827 version 8.3 tech sky130A style ngspice() @@ -21,61 +21,61 @@ node "D" 1470 418.74 -250 -140 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34600 2100 0 0 8000 400 0 0 0 0 0 0 0 0 0 0 0 0 node "w_n290_n40#" 7882 2692.8 -290 -40 nw 0 0 0 0 897600 4960 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -cap "Z1" "Z2" 709.991 -cap "VDD" "GND" 17.6 -cap "GND" "Z4" 527.304 -cap "Qbar1" "R" 11.3571 -cap "Q" "Qbar" 213.204 -cap "Qbar1" "Qbar" 7.54286 -cap "Z3" "R" 137.379 -cap "clk" "R" 508.778 -cap "Z3" "Z2" 249.04 -cap "D" "R" 16.14 -cap "Z3" "Z1" 85.3 -cap "clk" "Z2" 187.91 -cap "clk" "Z1" 170.927 +cap "clk" "Z3" 652.716 +cap "D" "clk" 31.5485 cap "w_n290_n40#" "Qbar" 1.85 -cap "D" "Z2" 47.3222 cap "w_n290_n40#" "Z2" 3.04 cap "w_n290_n40#" "Z1" 7.4 -cap "VDD" "Qbar" 237.6 -cap "Q" "z5" 33 -cap "VDD" "Z2" 95.0921 -cap "Qbar1" "z5" 203.056 -cap "Qbar1" "Q" 109.835 -cap "VDD" "Z1" 316.564 -cap "Z3" "z5" 110 -cap "Z3" "Q" 28.6775 -cap "clk" "z5" 38.3774 -cap "Z3" "Qbar1" 379.384 -cap "clk" "Qbar1" 121.715 -cap "R" "GND" 35.3744 -cap "w_n290_n40#" "Q" 1.85 -cap "clk" "Z3" 652.716 -cap "Qbar" "GND" 138.6 -cap "Z2" "Z4" 137.657 -cap "w_n290_n40#" "Qbar1" 1.82 -cap "Z2" "GND" 142.361 -cap "w_n290_n40#" "Z3" 11.56 -cap "D" "clk" 31.5485 -cap "w_n290_n40#" "clk" 10.355 -cap "VDD" "z5" 6.6 -cap "Q" "VDD" 334.95 -cap "Qbar1" "VDD" 315.732 -cap "Z3" "VDD" 509.325 -cap "clk" "VDD" 129.37 -cap "D" "VDD" 38.5 -cap "Z4" "z5" 42.0885 cap "w_n290_n40#" "VDD" 7.4 -cap "GND" "z5" 558.112 +cap "Q" "z5" 33 +cap "Qbar1" "z5" 203.056 +cap "Z3" "z5" 110 cap "Q" "GND" 263.95 cap "Z3" "Z4" 201.943 cap "Qbar1" "GND" 157.761 +cap "Qbar1" "R" 11.3571 +cap "clk" "z5" 38.3774 cap "Z3" "GND" 324.951 +cap "Q" "Qbar" 213.204 +cap "Qbar1" "Qbar" 7.54286 cap "clk" "Z4" 18.15 +cap "Z3" "R" 137.379 cap "clk" "GND" 37.5833 cap "D" "GND" 14.4375 +cap "Q" "VDD" 334.95 +cap "Z3" "Z2" 249.04 +cap "clk" "R" 508.778 +cap "Qbar1" "VDD" 315.732 +cap "Z3" "Z1" 85.3 +cap "D" "R" 16.14 +cap "Z3" "VDD" 509.325 +cap "clk" "Z2" 187.91 +cap "clk" "Z1" 170.927 +cap "D" "Z2" 47.3222 +cap "clk" "VDD" 129.37 +cap "D" "VDD" 38.5 +cap "Z4" "z5" 42.0885 +cap "w_n290_n40#" "Q" 1.85 +cap "w_n290_n40#" "Qbar1" 1.82 +cap "GND" "z5" 558.112 +cap "GND" "Z4" 527.304 +cap "w_n290_n40#" "Z3" 11.56 +cap "w_n290_n40#" "clk" 10.355 +cap "R" "GND" 35.3744 +cap "Qbar" "GND" 138.6 +cap "Z2" "Z4" 137.657 +cap "VDD" "z5" 6.6 +cap "Z2" "GND" 142.361 cap "Z2" "R" 208.97 +cap "VDD" "GND" 17.6 +cap "VDD" "Qbar" 237.6 +cap "Z1" "Z2" 709.991 +cap "Qbar1" "Q" 109.835 +cap "VDD" "Z2" 95.0921 +cap "Z3" "Q" 28.6775 +cap "VDD" "Z1" 316.564 +cap "Z3" "Qbar1" 379.384 +cap "clk" "Qbar1" 121.715 device msubckt sky130_fd_pr__nfet_01v8 1580 -480 1581 -479 l=30 w=180 "VSUBS" "Q" 60 0 "GND" 180 0 "Qbar" 180 0 device msubckt sky130_fd_pr__nfet_01v8 1330 -480 1331 -479 l=30 w=180 "VSUBS" "Qbar1" 60 0 "GND" 180 0 "Q" 180 0 device msubckt sky130_fd_pr__nfet_01v8 1080 -480 1081 -479 l=30 w=180 "VSUBS" "Z3" 60 0 "GND" 180 0 "z5" 180 0
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext index b929c85..cdc468b 100644 --- a/mag/user_analog_project_wrapper.ext +++ b/mag/user_analog_project_wrapper.ext
@@ -1,10 +1,15 @@ -timestamp 1640911630 +timestamp 1640959832 version 8.3 tech sky130A style ngspice() scale 1000 1 500000 resistclasses 4400000 2200000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5 use cp cp_1 1 0 531400 0 1 683270 +use cp cp_0 1 0 196464 0 1 608714 +use filter filter_0 1 0 224356 0 1 680484 +use divider divider_0 1 0 163690 0 1 648664 +use pd pd_0 1 0 87306 0 1 647408 +use ro_complete ro_complete_0 1 0 31596 0 1 681444 port "io_analog[4]" 41 329294 702300 334294 704800 m5 port "io_analog[4]" 47 318994 702300 323994 704800 m5 port "io_analog[5]" 42 227594 702300 232594 704800 m5 @@ -1388,6 +1393,13 @@ node "w_534690_682780#" 2061 2427.03 534690 682780 nw 0 0 0 0 171600 1660 0 0 78300 1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67500 1040 67500 1040 67500 1040 171600 1660 1425600 9300 0 0 0 0 node "w_534750_683750#" 17515 3366 534750 683750 nw 0 0 0 0 1122000 7460 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +cap "io_analog[3]" "vssa1" 6389.64 +cap "io_analog[1]" "io_analog[0]" 12301.4 +cap "io_analog[2]" "vssa1" 9275.17 +cap "io_clamp_high[0]" "io_analog[4]" 525 +cap "io_clamp_low[0]" "io_clamp_high[0]" 525 +cap "io_analog[4]" "io_clamp_low[0]" 525 +cap "w_534750_683750#" "w_534690_682780#" 224.4 cap "io_clamp_high[1]" "io_analog[5]" 525 cap "io_clamp_low[1]" "io_clamp_high[1]" 525 cap "io_analog[5]" "io_clamp_low[1]" 525 @@ -1399,37 +1411,30 @@ cap "io_analog[5]" "io_analog[5]" 26250 cap "io_analog[5]" "io_analog[5]" 26250 cap "io_analog[4]" "io_analog[4]" 21250 -cap "io_analog[1]" "io_analog[0]" 12301.4 cap "io_analog[6]" "io_analog[6]" 26250 cap "io_analog[4]" "io_analog[4]" 21250 cap "io_analog[5]" "io_analog[5]" 21250 cap "io_analog[6]" "io_analog[6]" 26250 +cap "io_analog[5]" "io_analog[5]" 21250 +cap "io_analog[6]" "io_analog[6]" 21250 +cap "io_analog[6]" "io_analog[6]" 21250 cap "io_analog[0]" "vdda1" 18313.2 cap "io_analog[1]" "vdda1" 23516.2 -cap "io_analog[5]" "io_analog[5]" 21250 cap "io_analog[2]" "vdda1" 219.25 -cap "io_analog[6]" "io_analog[6]" 21250 -cap "io_analog[3]" "vssa1" 6389.64 -cap "io_analog[2]" "vssa1" 9275.17 -cap "io_analog[6]" "io_analog[6]" 21250 -cap "w_534750_683750#" "w_534690_682780#" 224.4 -cap "io_clamp_high[0]" "io_analog[4]" 525 -cap "io_clamp_low[0]" "io_clamp_high[0]" 525 -cap "io_analog[4]" "io_clamp_low[0]" 525 cap "cp_1/gnd!" "cp_1/down" 439.89 cap "cp_1/gnd!" "io_analog[1]" -20.89 cap "cp_1/vbias" "cp_1/gnd!" 6.79412 cap "cp_1/vbias" "cp_1/gnd!" 8.73529 cap "cp_1/vbias" "cp_1/gnd!" 6.79412 -cap "cp_1/vbias" "cp_1/gnd!" 8.73529 +cap "cp_1/gnd!" "cp_1/vbias" 8.73529 cap "cp_1/a_10_n50#" "cp_1/vbias" 31.68 -cap "cp_1/a_1710_n2840#" "cp_1/a_1710_0#" 37.5 +cap "cp_1/a_1710_0#" "cp_1/a_1710_n2840#" 37.5 cap "cp_1/a_1710_n2840#" "cp_1/a_3060_0#" 99.11 cap "cp_1/a_1710_n2840#" "cp_1/a_3060_0#" 243.801 cap "cp_1/a_3060_0#" "w_534690_682780#" 1083.86 cap "w_534750_683750#" "w_534690_682780#" -39.04 +cap "w_534690_682780#" "w_534750_683750#" -28 cap "cp_1/a_3060_0#" "w_534690_682780#" 904.4 -cap "w_534750_683750#" "w_534690_682780#" -28 cap "cp_1/a_3060_0#" "w_534690_682780#" 50.49 cap "cp_1/a_3060_0#" "w_534690_682780#" 119.25 cap "w_534750_683750#" "w_534690_682780#" -15.96 @@ -1439,8 +1444,13 @@ merge "vdda1" "cp_1/vdd!" merge "cp_1/vdd!" "w_534690_682780#" merge "w_534690_682780#" "w_534750_683750#" -merge "cp_1/gnd!" "VSUBS" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0 -merge "VSUBS" "vssa1" +merge "cp_1/gnd!" "vssa1" -13903.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -24058574 -32614 0 0 0 0 0 0 +merge "vssa1" "ro_complete_0/a_7790_n10640#" +merge "ro_complete_0/a_7790_n10640#" "filter_0/v" +merge "filter_0/v" "divider_0/a_n940_n20#" +merge "divider_0/a_n940_n20#" "pd_0/a_n420_n1430#" +merge "pd_0/a_n420_n1430#" "cp_0/gnd!" +merge "cp_0/gnd!" "VSUBS" merge "cp_1/down" "io_analog[1]" -8142.87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -163500 -2410 -16700 -870 -226500 -1840 -12500000 -15000 0 0 0 0 0 0 merge "cp_1/vbias" "io_analog[3]" -6896.59 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65310 -480 0 0 0 0 -12500000 -15000 0 0 0 0 0 0 merge "cp_1/upbar" "io_analog[2]" -6942.45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 55080 -460 0 0 0 0 -12500000 -15000 0 0 0 0 0 0
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag index 0a66561..8e79934 100644 --- a/mag/user_analog_project_wrapper.mag +++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@ magic tech sky130A -timestamp 1640911630 +timestamp 1640959863 << nwell >> rect 267375 341875 267540 343575 rect 267345 341390 267565 341585 @@ -863,9 +863,29 @@ rect 292000 0 292050 352000 rect -50 -50 292050 0 use cp cp_1 -timestamp 1640911630 +timestamp 1640911461 transform 1 0 265700 0 1 341635 box -415 -1715 4690 2035 +use cp cp_0 +timestamp 1640911461 +transform 1 0 98232 0 1 304357 +box -415 -1715 4690 2035 +use filter filter_0 +timestamp 1640921877 +transform 1 0 112178 0 1 340242 +box -1800 -10450 6065 390 +use divider divider_0 +timestamp 1640959863 +transform 1 0 81845 0 1 324332 +box -490 -235 4690 2150 +use pd pd_0 +timestamp 1640959863 +transform 1 0 43653 0 1 323704 +box -215 -855 1685 810 +use ro_complete ro_complete_0 +timestamp 1640959832 +transform 1 0 15798 0 1 340722 +box -57 -5330 4455 1440 << labels >> flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0] port 0 nsew signal bidirectional
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice index 1806502..f5e5cb0 100644 --- a/netgen/user_analog_project_wrapper.spice +++ b/netgen/user_analog_project_wrapper.spice
@@ -106,688 +106,1215 @@ + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6] + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3] + wbs_stb_i wbs_we_i -C0 io_clamp_low[2] io_analog[6] 0.53fF -C1 io_analog[0] io_analog[1] 12.30fF -C2 cp_0/a_1710_0# io_analog[0] 0.84fF -C3 cp_0/a_10_n50# cp_0/a_1710_0# 0.04fF -C4 io_clamp_high[1] io_analog[5] 0.53fF -C5 cp_0/a_1710_0# io_analog[1] 0.32fF -C6 io_clamp_low[0] io_analog[4] 0.53fF -C7 io_clamp_low[2] io_clamp_high[2] 0.53fF -C8 io_clamp_low[1] io_clamp_high[1] 0.53fF -C9 io_clamp_high[2] io_analog[6] 0.53fF -C10 io_analog[2] io_analog[1] 0.02fF -C11 cp_0/a_10_n50# io_analog[3] 0.22fF -C12 io_clamp_low[1] io_analog[5] 0.53fF -C13 io_clamp_low[0] io_clamp_high[0] 0.53fF -C14 io_clamp_high[0] io_analog[4] 0.53fF -Xcp_0 io_analog[3] vdda1 vssa1 io_analog[0] io_analog[1] io_analog[2] cp -C15 io_analog[4] vdda1 25.05fF -C16 io_analog[5] vdda1 25.05fF -C17 io_analog[6] vdda1 25.05fF -C18 io_in_3v3[0] vdda1 0.61fF -C19 io_oeb[26] vdda1 0.61fF -C20 io_in[0] vdda1 0.61fF -C21 io_out[26] vdda1 0.61fF -C22 io_out[0] vdda1 0.61fF -C23 io_in[26] vdda1 0.61fF -C24 io_oeb[0] vdda1 0.61fF -C25 io_in_3v3[26] vdda1 0.61fF -C26 io_in_3v3[1] vdda1 0.61fF -C27 io_oeb[25] vdda1 0.61fF -C28 io_in[1] vdda1 0.61fF -C29 io_out[25] vdda1 0.61fF -C30 io_out[1] vdda1 0.61fF -C31 io_in[25] vdda1 0.61fF -C32 io_oeb[1] vdda1 0.61fF -C33 io_in_3v3[25] vdda1 0.61fF -C34 io_in_3v3[2] vdda1 0.61fF -C35 io_oeb[24] vdda1 0.61fF -C36 io_in[2] vdda1 0.61fF -C37 io_out[24] vdda1 0.61fF -C38 io_out[2] vdda1 0.61fF -C39 io_in[24] vdda1 0.61fF -C40 io_oeb[2] vdda1 0.61fF -C41 io_in_3v3[24] vdda1 0.61fF -C42 io_in_3v3[3] vdda1 0.61fF -C43 gpio_noesd[17] vdda1 0.61fF -C44 io_in[3] vdda1 0.61fF -C45 gpio_analog[17] vdda1 0.61fF -C46 io_out[3] vdda1 0.61fF -C47 io_oeb[3] vdda1 0.61fF -C48 io_in_3v3[4] vdda1 0.61fF -C49 io_in[4] vdda1 0.61fF -C50 io_out[4] vdda1 0.61fF -C51 io_oeb[4] vdda1 0.61fF -C52 io_oeb[23] vdda1 0.61fF -C53 io_out[23] vdda1 0.61fF -C54 io_in[23] vdda1 0.61fF -C55 io_in_3v3[23] vdda1 0.61fF -C56 gpio_noesd[16] vdda1 0.61fF -C57 gpio_analog[16] vdda1 0.61fF -C58 io_in_3v3[5] vdda1 0.61fF -C59 io_in[5] vdda1 0.61fF -C60 io_out[5] vdda1 0.61fF -C61 io_oeb[5] vdda1 0.61fF -C62 io_oeb[22] vdda1 0.61fF -C63 io_out[22] vdda1 0.61fF -C64 io_in[22] vdda1 0.61fF -C65 io_in_3v3[22] vdda1 0.61fF -C66 gpio_noesd[15] vdda1 0.61fF -C67 gpio_analog[15] vdda1 0.61fF -C68 io_in_3v3[6] vdda1 0.61fF -C69 io_in[6] vdda1 0.61fF -C70 io_out[6] vdda1 0.61fF -C71 io_oeb[6] vdda1 0.61fF -C72 io_oeb[21] vdda1 0.61fF -C73 io_out[21] vdda1 0.61fF -C74 io_in[21] vdda1 0.61fF -C75 io_in_3v3[21] vdda1 0.61fF -C76 gpio_noesd[14] vdda1 0.61fF -C77 gpio_analog[14] vdda1 0.61fF -C78 vssd2 vdda1 13.04fF -C79 vssd1 vdda1 13.04fF -C80 vdda2 vdda1 13.04fF -C81 io_oeb[20] vdda1 0.61fF -C82 io_out[20] vdda1 0.61fF -C83 io_in[20] vdda1 0.61fF -C84 io_in_3v3[20] vdda1 0.61fF -C85 gpio_noesd[13] vdda1 0.61fF -C86 gpio_analog[13] vdda1 0.61fF -C87 gpio_analog[0] vdda1 0.61fF -C88 gpio_noesd[0] vdda1 0.61fF -C89 io_in_3v3[7] vdda1 0.61fF -C90 io_in[7] vdda1 0.61fF -C91 io_out[7] vdda1 0.61fF -C92 io_oeb[7] vdda1 0.61fF -C93 io_oeb[19] vdda1 0.61fF -C94 io_out[19] vdda1 0.61fF -C95 io_in[19] vdda1 0.61fF -C96 io_in_3v3[19] vdda1 0.61fF -C97 gpio_noesd[12] vdda1 0.61fF -C98 gpio_analog[12] vdda1 0.61fF -C99 gpio_analog[1] vdda1 0.61fF -C100 gpio_noesd[1] vdda1 0.61fF -C101 io_in_3v3[8] vdda1 0.61fF -C102 io_in[8] vdda1 0.61fF -C103 io_out[8] vdda1 0.61fF -C104 io_oeb[8] vdda1 0.61fF -C105 io_oeb[18] vdda1 0.61fF -C106 io_out[18] vdda1 0.61fF -C107 io_in[18] vdda1 0.61fF -C108 io_in_3v3[18] vdda1 0.61fF -C109 gpio_noesd[11] vdda1 0.61fF -C110 gpio_analog[11] vdda1 0.61fF -C111 gpio_analog[2] vdda1 0.61fF -C112 gpio_noesd[2] vdda1 0.61fF -C113 io_in_3v3[9] vdda1 0.61fF -C114 io_in[9] vdda1 0.61fF -C115 io_out[9] vdda1 0.61fF -C116 io_oeb[9] vdda1 0.61fF -C117 io_oeb[17] vdda1 0.61fF -C118 io_out[17] vdda1 0.61fF -C119 io_in[17] vdda1 0.61fF -C120 io_in_3v3[17] vdda1 0.61fF -C121 gpio_noesd[10] vdda1 0.61fF -C122 gpio_analog[10] vdda1 0.61fF -C123 gpio_analog[3] vdda1 0.61fF -C124 gpio_noesd[3] vdda1 0.61fF -C125 io_in_3v3[10] vdda1 0.61fF -C126 io_in[10] vdda1 0.61fF -C127 io_out[10] vdda1 0.61fF -C128 io_oeb[10] vdda1 0.61fF -C129 io_oeb[16] vdda1 0.61fF -C130 io_out[16] vdda1 0.61fF -C131 io_in[16] vdda1 0.61fF -C132 io_in_3v3[16] vdda1 0.61fF -C133 gpio_noesd[9] vdda1 0.61fF -C134 gpio_analog[9] vdda1 0.61fF -C135 gpio_analog[4] vdda1 0.61fF -C136 gpio_noesd[4] vdda1 0.61fF -C137 io_in_3v3[11] vdda1 0.61fF -C138 io_in[11] vdda1 0.61fF -C139 io_out[11] vdda1 0.61fF -C140 io_oeb[11] vdda1 0.61fF -C141 io_oeb[15] vdda1 0.61fF -C142 io_out[15] vdda1 0.61fF -C143 io_in[15] vdda1 0.61fF -C144 io_in_3v3[15] vdda1 0.61fF -C145 gpio_noesd[8] vdda1 0.61fF -C146 gpio_analog[8] vdda1 0.61fF -C147 gpio_analog[5] vdda1 0.61fF -C148 gpio_noesd[5] vdda1 0.61fF -C149 io_in_3v3[12] vdda1 0.61fF -C150 io_in[12] vdda1 0.61fF -C151 io_out[12] vdda1 0.61fF -C152 io_oeb[12] vdda1 0.61fF -C153 io_oeb[14] vdda1 0.61fF -C154 io_out[14] vdda1 0.61fF -C155 io_in[14] vdda1 0.61fF -C156 io_in_3v3[14] vdda1 0.61fF -C157 gpio_noesd[7] vdda1 0.61fF -C158 gpio_analog[7] vdda1 0.61fF -C159 vssa2 vdda1 13.04fF -C160 gpio_analog[6] vdda1 0.61fF -C161 gpio_noesd[6] vdda1 0.61fF -C162 io_in_3v3[13] vdda1 0.61fF -C163 io_in[13] vdda1 0.61fF -C164 io_out[13] vdda1 0.61fF -C165 io_oeb[13] vdda1 0.61fF -C166 vccd1 vdda1 13.04fF -C167 vccd2 vdda1 13.04fF -C168 io_analog[10] vdda1 6.83fF -C169 io_clamp_high[0] vdda1 3.58fF -C170 io_clamp_low[0] vdda1 3.58fF -C171 io_clamp_high[1] vdda1 3.58fF -C172 io_clamp_low[1] vdda1 3.58fF -C173 io_clamp_high[2] vdda1 3.58fF -C174 io_clamp_low[2] vdda1 3.58fF -C175 io_analog[7] vdda1 6.83fF -C176 io_analog[8] vdda1 6.83fF -C177 io_analog[9] vdda1 6.83fF -C178 user_irq[2] vdda1 0.63fF -C179 user_irq[1] vdda1 0.63fF -C180 user_irq[0] vdda1 0.63fF -C181 user_clock2 vdda1 0.63fF -C182 la_oenb[127] vdda1 0.63fF -C183 la_data_out[127] vdda1 0.63fF -C184 la_data_in[127] vdda1 0.63fF -C185 la_oenb[126] vdda1 0.63fF -C186 la_data_out[126] vdda1 0.63fF -C187 la_data_in[126] vdda1 0.63fF -C188 la_oenb[125] vdda1 0.63fF -C189 la_data_out[125] vdda1 0.63fF -C190 la_data_in[125] vdda1 0.63fF -C191 la_oenb[124] vdda1 0.63fF -C192 la_data_out[124] vdda1 0.63fF -C193 la_data_in[124] vdda1 0.63fF -C194 la_oenb[123] vdda1 0.63fF -C195 la_data_out[123] vdda1 0.63fF -C196 la_data_in[123] vdda1 0.63fF -C197 la_oenb[122] vdda1 0.63fF -C198 la_data_out[122] vdda1 0.63fF -C199 la_data_in[122] vdda1 0.63fF -C200 la_oenb[121] vdda1 0.63fF -C201 la_data_out[121] vdda1 0.63fF -C202 la_data_in[121] vdda1 0.63fF -C203 la_oenb[120] vdda1 0.63fF -C204 la_data_out[120] vdda1 0.63fF -C205 la_data_in[120] vdda1 0.63fF -C206 la_oenb[119] vdda1 0.63fF -C207 la_data_out[119] vdda1 0.63fF -C208 la_data_in[119] vdda1 0.63fF -C209 la_oenb[118] vdda1 0.63fF -C210 la_data_out[118] vdda1 0.63fF -C211 la_data_in[118] vdda1 0.63fF -C212 la_oenb[117] vdda1 0.63fF -C213 la_data_out[117] vdda1 0.63fF -C214 la_data_in[117] vdda1 0.63fF -C215 la_oenb[116] vdda1 0.63fF -C216 la_data_out[116] vdda1 0.63fF -C217 la_data_in[116] vdda1 0.63fF -C218 la_oenb[115] vdda1 0.63fF -C219 la_data_out[115] vdda1 0.63fF -C220 la_data_in[115] vdda1 0.63fF -C221 la_oenb[114] vdda1 0.63fF -C222 la_data_out[114] vdda1 0.63fF -C223 la_data_in[114] vdda1 0.63fF -C224 la_oenb[113] vdda1 0.63fF -C225 la_data_out[113] vdda1 0.63fF -C226 la_data_in[113] vdda1 0.63fF -C227 la_oenb[112] vdda1 0.63fF -C228 la_data_out[112] vdda1 0.63fF -C229 la_data_in[112] vdda1 0.63fF -C230 la_oenb[111] vdda1 0.63fF -C231 la_data_out[111] vdda1 0.63fF -C232 la_data_in[111] vdda1 0.63fF -C233 la_oenb[110] vdda1 0.63fF -C234 la_data_out[110] vdda1 0.63fF -C235 la_data_in[110] vdda1 0.63fF -C236 la_oenb[109] vdda1 0.63fF -C237 la_data_out[109] vdda1 0.63fF -C238 la_data_in[109] vdda1 0.63fF -C239 la_oenb[108] vdda1 0.63fF -C240 la_data_out[108] vdda1 0.63fF -C241 la_data_in[108] vdda1 0.63fF -C242 la_oenb[107] vdda1 0.63fF -C243 la_data_out[107] vdda1 0.63fF -C244 la_data_in[107] vdda1 0.63fF -C245 la_oenb[106] vdda1 0.63fF -C246 la_data_out[106] vdda1 0.63fF -C247 la_data_in[106] vdda1 0.63fF -C248 la_oenb[105] vdda1 0.63fF -C249 la_data_out[105] vdda1 0.63fF -C250 la_data_in[105] vdda1 0.63fF -C251 la_oenb[104] vdda1 0.63fF -C252 la_data_out[104] vdda1 0.63fF -C253 la_data_in[104] vdda1 0.63fF -C254 la_oenb[103] vdda1 0.63fF -C255 la_data_out[103] vdda1 0.63fF -C256 la_data_in[103] vdda1 0.63fF -C257 la_oenb[102] vdda1 0.63fF -C258 la_data_out[102] vdda1 0.63fF -C259 la_data_in[102] vdda1 0.63fF -C260 la_oenb[101] vdda1 0.63fF -C261 la_data_out[101] vdda1 0.63fF -C262 la_data_in[101] vdda1 0.63fF -C263 la_oenb[100] vdda1 0.63fF -C264 la_data_out[100] vdda1 0.63fF -C265 la_data_in[100] vdda1 0.63fF -C266 la_oenb[99] vdda1 0.63fF -C267 la_data_out[99] vdda1 0.63fF -C268 la_data_in[99] vdda1 0.63fF -C269 la_oenb[98] vdda1 0.63fF -C270 la_data_out[98] vdda1 0.63fF -C271 la_data_in[98] vdda1 0.63fF -C272 la_oenb[97] vdda1 0.63fF -C273 la_data_out[97] vdda1 0.63fF -C274 la_data_in[97] vdda1 0.63fF -C275 la_oenb[96] vdda1 0.63fF -C276 la_data_out[96] vdda1 0.63fF -C277 la_data_in[96] vdda1 0.63fF -C278 la_oenb[95] vdda1 0.63fF -C279 la_data_out[95] vdda1 0.63fF -C280 la_data_in[95] vdda1 0.63fF -C281 la_oenb[94] vdda1 0.63fF -C282 la_data_out[94] vdda1 0.63fF -C283 la_data_in[94] vdda1 0.63fF -C284 la_oenb[93] vdda1 0.63fF -C285 la_data_out[93] vdda1 0.63fF -C286 la_data_in[93] vdda1 0.63fF -C287 la_oenb[92] vdda1 0.63fF -C288 la_data_out[92] vdda1 0.63fF -C289 la_data_in[92] vdda1 0.63fF -C290 la_oenb[91] vdda1 0.63fF -C291 la_data_out[91] vdda1 0.63fF -C292 la_data_in[91] vdda1 0.63fF -C293 la_oenb[90] vdda1 0.63fF -C294 la_data_out[90] vdda1 0.63fF -C295 la_data_in[90] vdda1 0.63fF -C296 la_oenb[89] vdda1 0.63fF -C297 la_data_out[89] vdda1 0.63fF -C298 la_data_in[89] vdda1 0.63fF -C299 la_oenb[88] vdda1 0.63fF -C300 la_data_out[88] vdda1 0.63fF -C301 la_data_in[88] vdda1 0.63fF -C302 la_oenb[87] vdda1 0.63fF -C303 la_data_out[87] vdda1 0.63fF -C304 la_data_in[87] vdda1 0.63fF -C305 la_oenb[86] vdda1 0.63fF -C306 la_data_out[86] vdda1 0.63fF -C307 la_data_in[86] vdda1 0.63fF -C308 la_oenb[85] vdda1 0.63fF -C309 la_data_out[85] vdda1 0.63fF -C310 la_data_in[85] vdda1 0.63fF -C311 la_oenb[84] vdda1 0.63fF -C312 la_data_out[84] vdda1 0.63fF -C313 la_data_in[84] vdda1 0.63fF -C314 la_oenb[83] vdda1 0.63fF -C315 la_data_out[83] vdda1 0.63fF -C316 la_data_in[83] vdda1 0.63fF -C317 la_oenb[82] vdda1 0.63fF -C318 la_data_out[82] vdda1 0.63fF -C319 la_data_in[82] vdda1 0.63fF -C320 la_oenb[81] vdda1 0.63fF -C321 la_data_out[81] vdda1 0.63fF -C322 la_data_in[81] vdda1 0.63fF -C323 la_oenb[80] vdda1 0.63fF -C324 la_data_out[80] vdda1 0.63fF -C325 la_data_in[80] vdda1 0.63fF -C326 la_oenb[79] vdda1 0.63fF -C327 la_data_out[79] vdda1 0.63fF -C328 la_data_in[79] vdda1 0.63fF -C329 la_oenb[78] vdda1 0.63fF -C330 la_data_out[78] vdda1 0.63fF -C331 la_data_in[78] vdda1 0.63fF -C332 la_oenb[77] vdda1 0.63fF -C333 la_data_out[77] vdda1 0.63fF -C334 la_data_in[77] vdda1 0.63fF -C335 la_oenb[76] vdda1 0.63fF -C336 la_data_out[76] vdda1 0.63fF -C337 la_data_in[76] vdda1 0.63fF -C338 la_oenb[75] vdda1 0.63fF -C339 la_data_out[75] vdda1 0.63fF -C340 la_data_in[75] vdda1 0.63fF -C341 la_oenb[74] vdda1 0.63fF -C342 la_data_out[74] vdda1 0.63fF -C343 la_data_in[74] vdda1 0.63fF -C344 la_oenb[73] vdda1 0.63fF -C345 la_data_out[73] vdda1 0.63fF -C346 la_data_in[73] vdda1 0.63fF -C347 la_oenb[72] vdda1 0.63fF -C348 la_data_out[72] vdda1 0.63fF -C349 la_data_in[72] vdda1 0.63fF -C350 la_oenb[71] vdda1 0.63fF -C351 la_data_out[71] vdda1 0.63fF -C352 la_data_in[71] vdda1 0.63fF -C353 la_oenb[70] vdda1 0.63fF -C354 la_data_out[70] vdda1 0.63fF -C355 la_data_in[70] vdda1 0.63fF -C356 la_oenb[69] vdda1 0.63fF -C357 la_data_out[69] vdda1 0.63fF -C358 la_data_in[69] vdda1 0.63fF -C359 la_oenb[68] vdda1 0.63fF -C360 la_data_out[68] vdda1 0.63fF -C361 la_data_in[68] vdda1 0.63fF -C362 la_oenb[67] vdda1 0.63fF -C363 la_data_out[67] vdda1 0.63fF -C364 la_data_in[67] vdda1 0.63fF -C365 la_oenb[66] vdda1 0.63fF -C366 la_data_out[66] vdda1 0.63fF -C367 la_data_in[66] vdda1 0.63fF -C368 la_oenb[65] vdda1 0.63fF -C369 la_data_out[65] vdda1 0.63fF -C370 la_data_in[65] vdda1 0.63fF -C371 la_oenb[64] vdda1 0.63fF -C372 la_data_out[64] vdda1 0.63fF -C373 la_data_in[64] vdda1 0.63fF -C374 la_oenb[63] vdda1 0.63fF -C375 la_data_out[63] vdda1 0.63fF -C376 la_data_in[63] vdda1 0.63fF -C377 la_oenb[62] vdda1 0.63fF -C378 la_data_out[62] vdda1 0.63fF -C379 la_data_in[62] vdda1 0.63fF -C380 la_oenb[61] vdda1 0.63fF -C381 la_data_out[61] vdda1 0.63fF -C382 la_data_in[61] vdda1 0.63fF -C383 la_oenb[60] vdda1 0.63fF -C384 la_data_out[60] vdda1 0.63fF -C385 la_data_in[60] vdda1 0.63fF -C386 la_oenb[59] vdda1 0.63fF -C387 la_data_out[59] vdda1 0.63fF -C388 la_data_in[59] vdda1 0.63fF -C389 la_oenb[58] vdda1 0.63fF -C390 la_data_out[58] vdda1 0.63fF -C391 la_data_in[58] vdda1 0.63fF -C392 la_oenb[57] vdda1 0.63fF -C393 la_data_out[57] vdda1 0.63fF -C394 la_data_in[57] vdda1 0.63fF -C395 la_oenb[56] vdda1 0.63fF -C396 la_data_out[56] vdda1 0.63fF -C397 la_data_in[56] vdda1 0.63fF -C398 la_oenb[55] vdda1 0.63fF -C399 la_data_out[55] vdda1 0.63fF -C400 la_data_in[55] vdda1 0.63fF -C401 la_oenb[54] vdda1 0.63fF -C402 la_data_out[54] vdda1 0.63fF -C403 la_data_in[54] vdda1 0.63fF -C404 la_oenb[53] vdda1 0.63fF -C405 la_data_out[53] vdda1 0.63fF -C406 la_data_in[53] vdda1 0.63fF -C407 la_oenb[52] vdda1 0.63fF -C408 la_data_out[52] vdda1 0.63fF -C409 la_data_in[52] vdda1 0.63fF -C410 la_oenb[51] vdda1 0.63fF -C411 la_data_out[51] vdda1 0.63fF -C412 la_data_in[51] vdda1 0.63fF -C413 la_oenb[50] vdda1 0.63fF -C414 la_data_out[50] vdda1 0.63fF -C415 la_data_in[50] vdda1 0.63fF -C416 la_oenb[49] vdda1 0.63fF -C417 la_data_out[49] vdda1 0.63fF -C418 la_data_in[49] vdda1 0.63fF -C419 la_oenb[48] vdda1 0.63fF -C420 la_data_out[48] vdda1 0.63fF -C421 la_data_in[48] vdda1 0.63fF -C422 la_oenb[47] vdda1 0.63fF -C423 la_data_out[47] vdda1 0.63fF -C424 la_data_in[47] vdda1 0.63fF -C425 la_oenb[46] vdda1 0.63fF -C426 la_data_out[46] vdda1 0.63fF -C427 la_data_in[46] vdda1 0.63fF -C428 la_oenb[45] vdda1 0.63fF -C429 la_data_out[45] vdda1 0.63fF -C430 la_data_in[45] vdda1 0.63fF -C431 la_oenb[44] vdda1 0.63fF -C432 la_data_out[44] vdda1 0.63fF -C433 la_data_in[44] vdda1 0.63fF -C434 la_oenb[43] vdda1 0.63fF -C435 la_data_out[43] vdda1 0.63fF -C436 la_data_in[43] vdda1 0.63fF -C437 la_oenb[42] vdda1 0.63fF -C438 la_data_out[42] vdda1 0.63fF -C439 la_data_in[42] vdda1 0.63fF -C440 la_oenb[41] vdda1 0.63fF -C441 la_data_out[41] vdda1 0.63fF -C442 la_data_in[41] vdda1 0.63fF -C443 la_oenb[40] vdda1 0.63fF -C444 la_data_out[40] vdda1 0.63fF -C445 la_data_in[40] vdda1 0.63fF -C446 la_oenb[39] vdda1 0.63fF -C447 la_data_out[39] vdda1 0.63fF -C448 la_data_in[39] vdda1 0.63fF -C449 la_oenb[38] vdda1 0.63fF -C450 la_data_out[38] vdda1 0.63fF -C451 la_data_in[38] vdda1 0.63fF -C452 la_oenb[37] vdda1 0.63fF -C453 la_data_out[37] vdda1 0.63fF -C454 la_data_in[37] vdda1 0.63fF -C455 la_oenb[36] vdda1 0.63fF -C456 la_data_out[36] vdda1 0.63fF -C457 la_data_in[36] vdda1 0.63fF -C458 la_oenb[35] vdda1 0.63fF -C459 la_data_out[35] vdda1 0.63fF -C460 la_data_in[35] vdda1 0.63fF -C461 la_oenb[34] vdda1 0.63fF -C462 la_data_out[34] vdda1 0.63fF -C463 la_data_in[34] vdda1 0.63fF -C464 la_oenb[33] vdda1 0.63fF -C465 la_data_out[33] vdda1 0.63fF -C466 la_data_in[33] vdda1 0.63fF -C467 la_oenb[32] vdda1 0.63fF -C468 la_data_out[32] vdda1 0.63fF -C469 la_data_in[32] vdda1 0.63fF -C470 la_oenb[31] vdda1 0.63fF -C471 la_data_out[31] vdda1 0.63fF -C472 la_data_in[31] vdda1 0.63fF -C473 la_oenb[30] vdda1 0.63fF -C474 la_data_out[30] vdda1 0.63fF -C475 la_data_in[30] vdda1 0.63fF -C476 la_oenb[29] vdda1 0.63fF -C477 la_data_out[29] vdda1 0.63fF -C478 la_data_in[29] vdda1 0.63fF -C479 la_oenb[28] vdda1 0.63fF -C480 la_data_out[28] vdda1 0.63fF -C481 la_data_in[28] vdda1 0.63fF -C482 la_oenb[27] vdda1 0.63fF -C483 la_data_out[27] vdda1 0.63fF -C484 la_data_in[27] vdda1 0.63fF -C485 la_oenb[26] vdda1 0.63fF -C486 la_data_out[26] vdda1 0.63fF -C487 la_data_in[26] vdda1 0.63fF -C488 la_oenb[25] vdda1 0.63fF -C489 la_data_out[25] vdda1 0.63fF -C490 la_data_in[25] vdda1 0.63fF -C491 la_oenb[24] vdda1 0.63fF -C492 la_data_out[24] vdda1 0.63fF -C493 la_data_in[24] vdda1 0.63fF -C494 la_oenb[23] vdda1 0.63fF -C495 la_data_out[23] vdda1 0.63fF -C496 la_data_in[23] vdda1 0.63fF -C497 la_oenb[22] vdda1 0.63fF -C498 la_data_out[22] vdda1 0.63fF -C499 la_data_in[22] vdda1 0.63fF -C500 la_oenb[21] vdda1 0.63fF -C501 la_data_out[21] vdda1 0.63fF -C502 la_data_in[21] vdda1 0.63fF -C503 la_oenb[20] vdda1 0.63fF -C504 la_data_out[20] vdda1 0.63fF -C505 la_data_in[20] vdda1 0.63fF -C506 la_oenb[19] vdda1 0.63fF -C507 la_data_out[19] vdda1 0.63fF -C508 la_data_in[19] vdda1 0.63fF -C509 la_oenb[18] vdda1 0.63fF -C510 la_data_out[18] vdda1 0.63fF -C511 la_data_in[18] vdda1 0.63fF -C512 la_oenb[17] vdda1 0.63fF -C513 la_data_out[17] vdda1 0.63fF -C514 la_data_in[17] vdda1 0.63fF -C515 la_oenb[16] vdda1 0.63fF -C516 la_data_out[16] vdda1 0.63fF -C517 la_data_in[16] vdda1 0.63fF -C518 la_oenb[15] vdda1 0.63fF -C519 la_data_out[15] vdda1 0.63fF -C520 la_data_in[15] vdda1 0.63fF -C521 la_oenb[14] vdda1 0.63fF -C522 la_data_out[14] vdda1 0.63fF -C523 la_data_in[14] vdda1 0.63fF -C524 la_oenb[13] vdda1 0.63fF -C525 la_data_out[13] vdda1 0.63fF -C526 la_data_in[13] vdda1 0.63fF -C527 la_oenb[12] vdda1 0.63fF -C528 la_data_out[12] vdda1 0.63fF -C529 la_data_in[12] vdda1 0.63fF -C530 la_oenb[11] vdda1 0.63fF -C531 la_data_out[11] vdda1 0.63fF -C532 la_data_in[11] vdda1 0.63fF -C533 la_oenb[10] vdda1 0.63fF -C534 la_data_out[10] vdda1 0.63fF -C535 la_data_in[10] vdda1 0.63fF -C536 la_oenb[9] vdda1 0.63fF -C537 la_data_out[9] vdda1 0.63fF -C538 la_data_in[9] vdda1 0.63fF -C539 la_oenb[8] vdda1 0.63fF -C540 la_data_out[8] vdda1 0.63fF -C541 la_data_in[8] vdda1 0.63fF -C542 la_oenb[7] vdda1 0.63fF -C543 la_data_out[7] vdda1 0.63fF -C544 la_data_in[7] vdda1 0.63fF -C545 la_oenb[6] vdda1 0.63fF -C546 la_data_out[6] vdda1 0.63fF -C547 la_data_in[6] vdda1 0.63fF -C548 la_oenb[5] vdda1 0.63fF -C549 la_data_out[5] vdda1 0.63fF -C550 la_data_in[5] vdda1 0.63fF -C551 la_oenb[4] vdda1 0.63fF -C552 la_data_out[4] vdda1 0.63fF -C553 la_data_in[4] vdda1 0.63fF -C554 la_oenb[3] vdda1 0.63fF -C555 la_data_out[3] vdda1 0.63fF -C556 la_data_in[3] vdda1 0.63fF -C557 la_oenb[2] vdda1 0.63fF -C558 la_data_out[2] vdda1 0.63fF -C559 la_data_in[2] vdda1 0.63fF -C560 la_oenb[1] vdda1 0.63fF -C561 la_data_out[1] vdda1 0.63fF -C562 la_data_in[1] vdda1 0.63fF -C563 la_oenb[0] vdda1 0.63fF -C564 la_data_out[0] vdda1 0.63fF -C565 la_data_in[0] vdda1 0.63fF -C566 wbs_dat_o[31] vdda1 0.63fF -C567 wbs_dat_i[31] vdda1 0.63fF -C568 wbs_adr_i[31] vdda1 0.63fF -C569 wbs_dat_o[30] vdda1 0.63fF -C570 wbs_dat_i[30] vdda1 0.63fF -C571 wbs_adr_i[30] vdda1 0.63fF -C572 wbs_dat_o[29] vdda1 0.63fF -C573 wbs_dat_i[29] vdda1 0.63fF -C574 wbs_adr_i[29] vdda1 0.63fF -C575 wbs_dat_o[28] vdda1 0.63fF -C576 wbs_dat_i[28] vdda1 0.63fF -C577 wbs_adr_i[28] vdda1 0.63fF -C578 wbs_dat_o[27] vdda1 0.63fF -C579 wbs_dat_i[27] vdda1 0.63fF -C580 wbs_adr_i[27] vdda1 0.63fF -C581 wbs_dat_o[26] vdda1 0.63fF -C582 wbs_dat_i[26] vdda1 0.63fF -C583 wbs_adr_i[26] vdda1 0.63fF -C584 wbs_dat_o[25] vdda1 0.63fF -C585 wbs_dat_i[25] vdda1 0.63fF -C586 wbs_adr_i[25] vdda1 0.63fF -C587 wbs_dat_o[24] vdda1 0.63fF -C588 wbs_dat_i[24] vdda1 0.63fF -C589 wbs_adr_i[24] vdda1 0.63fF -C590 wbs_dat_o[23] vdda1 0.63fF -C591 wbs_dat_i[23] vdda1 0.63fF -C592 wbs_adr_i[23] vdda1 0.63fF -C593 wbs_dat_o[22] vdda1 0.63fF -C594 wbs_dat_i[22] vdda1 0.63fF -C595 wbs_adr_i[22] vdda1 0.63fF -C596 wbs_dat_o[21] vdda1 0.63fF -C597 wbs_dat_i[21] vdda1 0.63fF -C598 wbs_adr_i[21] vdda1 0.63fF -C599 wbs_dat_o[20] vdda1 0.63fF -C600 wbs_dat_i[20] vdda1 0.63fF -C601 wbs_adr_i[20] vdda1 0.63fF -C602 wbs_dat_o[19] vdda1 0.63fF -C603 wbs_dat_i[19] vdda1 0.63fF -C604 wbs_adr_i[19] vdda1 0.63fF -C605 wbs_dat_o[18] vdda1 0.63fF -C606 wbs_dat_i[18] vdda1 0.63fF -C607 wbs_adr_i[18] vdda1 0.63fF -C608 wbs_dat_o[17] vdda1 0.63fF -C609 wbs_dat_i[17] vdda1 0.63fF -C610 wbs_adr_i[17] vdda1 0.63fF -C611 wbs_dat_o[16] vdda1 0.63fF -C612 wbs_dat_i[16] vdda1 0.63fF -C613 wbs_adr_i[16] vdda1 0.63fF -C614 wbs_dat_o[15] vdda1 0.63fF -C615 wbs_dat_i[15] vdda1 0.63fF -C616 wbs_adr_i[15] vdda1 0.63fF -C617 wbs_dat_o[14] vdda1 0.63fF -C618 wbs_dat_i[14] vdda1 0.63fF -C619 wbs_adr_i[14] vdda1 0.63fF -C620 wbs_dat_o[13] vdda1 0.63fF -C621 wbs_dat_i[13] vdda1 0.63fF -C622 wbs_adr_i[13] vdda1 0.63fF -C623 wbs_dat_o[12] vdda1 0.63fF -C624 wbs_dat_i[12] vdda1 0.63fF -C625 wbs_adr_i[12] vdda1 0.63fF -C626 wbs_dat_o[11] vdda1 0.63fF -C627 wbs_dat_i[11] vdda1 0.63fF -C628 wbs_adr_i[11] vdda1 0.63fF -C629 wbs_dat_o[10] vdda1 0.63fF -C630 wbs_dat_i[10] vdda1 0.63fF -C631 wbs_adr_i[10] vdda1 0.63fF -C632 wbs_dat_o[9] vdda1 0.63fF -C633 wbs_dat_i[9] vdda1 0.63fF -C634 wbs_adr_i[9] vdda1 0.63fF -C635 wbs_dat_o[8] vdda1 0.63fF -C636 wbs_dat_i[8] vdda1 0.63fF -C637 wbs_adr_i[8] vdda1 0.63fF -C638 wbs_dat_o[7] vdda1 0.63fF -C639 wbs_dat_i[7] vdda1 0.63fF -C640 wbs_adr_i[7] vdda1 0.63fF -C641 wbs_dat_o[6] vdda1 0.63fF -C642 wbs_dat_i[6] vdda1 0.63fF -C643 wbs_adr_i[6] vdda1 0.63fF -C644 wbs_dat_o[5] vdda1 0.63fF -C645 wbs_dat_i[5] vdda1 0.63fF -C646 wbs_adr_i[5] vdda1 0.63fF -C647 wbs_dat_o[4] vdda1 0.63fF -C648 wbs_dat_i[4] vdda1 0.63fF -C649 wbs_adr_i[4] vdda1 0.63fF -C650 wbs_sel_i[3] vdda1 0.63fF -C651 wbs_dat_o[3] vdda1 0.63fF -C652 wbs_dat_i[3] vdda1 0.63fF -C653 wbs_adr_i[3] vdda1 0.63fF -C654 wbs_sel_i[2] vdda1 0.63fF -C655 wbs_dat_o[2] vdda1 0.63fF -C656 wbs_dat_i[2] vdda1 0.63fF -C657 wbs_adr_i[2] vdda1 0.63fF -C658 wbs_sel_i[1] vdda1 0.63fF -C659 wbs_dat_o[1] vdda1 0.63fF -C660 wbs_dat_i[1] vdda1 0.63fF -C661 wbs_adr_i[1] vdda1 0.63fF -C662 wbs_sel_i[0] vdda1 0.63fF -C663 wbs_dat_o[0] vdda1 0.63fF -C664 wbs_dat_i[0] vdda1 0.63fF -C665 wbs_adr_i[0] vdda1 0.63fF -C666 wbs_we_i vdda1 0.63fF -C667 wbs_stb_i vdda1 0.63fF -C668 wbs_cyc_i vdda1 0.63fF -C669 wbs_ack_o vdda1 0.63fF -C670 wb_rst_i vdda1 0.63fF -C671 wb_clk_i vdda1 0.63fF -C672 io_analog[1] vdda1 108.63fF -C673 io_analog[3] vdda1 197.37fF -C674 io_analog[0] vdda1 74.25fF -C675 io_analog[2] vdda1 108.15fF -C676 cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING -C677 cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING -C678 cp_0/a_7110_0# vdda1 0.17fF **FLOATING -C679 cp_0/a_6370_0# vdda1 0.40fF **FLOATING -C680 cp_0/a_3060_0# vdda1 4.15fF **FLOATING -C681 cp_0/a_1710_0# vdda1 6.63fF **FLOATING -C682 cp_0/a_10_n50# vdda1 2.96fF **FLOATING +C0 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF +C1 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF +C2 gnd divider_0/clk 0.07fF +C3 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF +C4 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF +C5 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF +C6 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF +C7 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF +C8 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF +C9 divider_0/mc2 divider_0/and_0/out1 0.06fF +C10 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF +C11 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF +C12 divider_0/prescaler_0/tspc_2/Z3 gnd 0.27fF +C13 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF +C14 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C15 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF +C16 divider_0/and_0/OUT divider_0/clk 0.04fF +C17 gnd divider_0/nor_0/B 1.08fF +C18 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF +C19 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF +C20 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF +C21 divider_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.45fF +C22 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF +C23 pd_0/R pd_0/UP 0.45fF +C24 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF +C25 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF +C26 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF +C27 divider_0/prescaler_0/tspc_1/Z4 gnd 0.44fF +C28 pd_0/UP pd_0/and_pd_0/Out1 0.33fF +C29 divider_0/nor_1/A divider_0/tspc_0/Z4 0.21fF +C30 divider_0/prescaler_0/tspc_1/Q gnd 0.83fF +C31 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF +C32 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF +C33 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF +C34 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF +C35 divider_0/tspc_2/Z3 divider_0/Out 0.05fF +C36 gnd divider_0/tspc_0/Z4 0.44fF +C37 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF +C38 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF +C39 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C40 divider_0/and_0/A divider_0/and_0/B 0.18fF +C41 io_clamp_low[1] io_clamp_high[1] 0.53fF +C42 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF +C43 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF +C44 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF +C45 divider_0/prescaler_0/tspc_2/Z4 gnd 0.44fF +C46 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF +C47 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF +C48 gnd divider_0/tspc_2/Z2 0.16fF +C49 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF +C50 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF +C51 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF +C52 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF +C53 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF +C54 io_clamp_high[2] io_analog[6] 0.53fF +C55 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF +C56 divider_0/tspc_1/Z3 gnd 0.27fF +C57 divider_0/mc2 divider_0/nor_0/B 0.15fF +C58 cp_0/upbar cp_0/down 0.02fF +C59 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF +C60 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF +C61 divider_0/prescaler_0/tspc_0/Q gnd 0.35fF +C62 divider_0/nor_1/A divider_0/and_0/A 0.01fF +C63 io_analog[2] io_analog[1] 0.02fF +C64 gnd divider_0/and_0/A 0.53fF +C65 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF +C66 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF +C67 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF +C68 pd_0/REF pd_0/tspc_r_1/z5 0.04fF +C69 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF +C70 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF +C71 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF +C72 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF +C73 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF +C74 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF +C75 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF +C76 gnd divider_0/Out 0.29fF +C77 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF +C78 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF +C79 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF +C80 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF +C81 io_clamp_low[1] io_analog[5] 0.53fF +C82 divider_0/nor_1/B divider_0/tspc_0/Q 0.22fF +C83 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF +C84 divider_0/prescaler_0/tspc_2/a_740_n680# gnd 0.22fF +C85 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF +C86 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF +C87 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF +C88 divider_0/tspc_0/Z2 divider_0/prescaler_0/Out 0.11fF +C89 divider_0/prescaler_0/tspc_2/D gnd 0.05fF +C90 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF +C91 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF +C92 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C93 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C94 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF +C95 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF +C96 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF +C97 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF +C98 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF +C99 divider_0/and_0/B divider_0/and_0/Z1 0.07fF +C100 io_clamp_low[0] io_clamp_high[0] 0.53fF +C101 pd_0/R pd_0/and_pd_0/Z1 0.02fF +C102 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF +C103 divider_0/prescaler_0/tspc_0/a_740_n680# gnd 0.22fF +C104 divider_0/mc2 divider_0/and_0/A 0.16fF +C105 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF +C106 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF +C107 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF +C108 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF +C109 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF +C110 divider_0/prescaler_0/tspc_0/Z2 gnd 0.16fF +C111 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF +C112 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF +C113 pd_0/DIV pd_0/R 0.51fF +C114 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF +C115 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF +C116 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF +C117 divider_0/and_0/out1 divider_0/and_0/A 0.01fF +C118 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF +C119 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF +C120 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF +C121 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF +C122 divider_0/prescaler_0/tspc_2/a_630_n680# gnd 0.63fF +C123 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF +C124 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF +C125 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF +C126 gnd divider_0/prescaler_0/nand_1/z1 0.16fF +C127 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF +C128 cp_1/a_10_n50# cp_1/a_1710_0# 0.04fF +C129 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF +C130 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF +C131 gnd divider_0/and_0/Z1 0.41fF +C132 pd_0/DOWN pd_0/UP 0.46fF +C133 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF +C134 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF +C135 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF +C136 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF +C137 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF +C138 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF +C139 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF +C140 divider_0/tspc_1/Z2 divider_0/tspc_0/Q 0.14fF +C141 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF +C142 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF +C143 divider_0/tspc_0/Z3 gnd 0.27fF +C144 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF +C145 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF +C146 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF +C147 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF +C148 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF +C149 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF +C150 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF +C151 divider_0/prescaler_0/tspc_0/Z4 gnd 0.44fF +C152 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF +C153 io_clamp_high[0] io_analog[4] 0.53fF +C154 divider_0/nor_1/B divider_0/and_0/B 0.31fF +C155 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF +C156 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF +C157 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF +C158 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF +C159 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF +C160 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF +C161 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF +C162 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF +C163 divider_0/tspc_1/Z4 divider_0/tspc_0/Q 0.15fF +C164 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF +C165 pd_0/R pd_0/REF 0.61fF +C166 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF +C167 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF +C168 divider_0/tspc_1/a_630_n680# divider_0/tspc_0/Q 0.01fF +C169 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF +C170 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF +C171 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF +C172 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF +C173 io_analog[0] cp_1/a_1710_0# 0.84fF +C174 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF +C175 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF +C176 divider_0/nor_1/B divider_0/nor_1/A 1.21fF +C177 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF +C178 divider_0/nor_0/B divider_0/Out 0.22fF +C179 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF +C180 gnd divider_0/prescaler_0/Out 0.46fF +C181 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF +C182 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF +C183 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF +C184 divider_0/nor_1/B gnd 1.10fF +C185 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF +C186 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF +C187 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF +C188 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF +C189 divider_0/prescaler_0/tspc_2/Z2 gnd 0.16fF +C190 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF +C191 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF +C192 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF +C193 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF +C194 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF +C195 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF +C196 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF +C197 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.01fF +C198 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF +C199 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF +C200 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF +C201 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF +C202 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF +C203 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF +C204 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF +C205 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF +C206 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF +C207 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF +C208 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF +C209 divider_0/nor_1/A divider_0/tspc_0/Q 0.55fF +C210 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF +C211 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF +C212 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF +C213 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF +C214 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF +C215 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF +C216 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF +C217 gnd divider_0/tspc_0/Q 0.33fF +C218 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF +C219 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF +C220 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF +C221 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF +C222 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF +C223 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF +C224 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF +C225 divider_0/prescaler_0/m1_2700_2190# gnd 0.22fF +C226 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF +C227 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF +C228 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF +C229 divider_0/tspc_0/Z2 gnd 0.16fF +C230 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF +C231 divider_0/nor_1/B divider_0/mc2 0.06fF +C232 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF +C233 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Q 0.04fF +C234 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF +C235 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF +C236 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF +C237 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF +C238 divider_0/prescaler_0/tspc_0/a_630_n680# gnd 0.61fF +C239 io_clamp_low[2] io_analog[6] 0.53fF +C240 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF +C241 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF +C242 divider_0/tspc_1/Z2 gnd 0.16fF +C243 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF +C244 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF +C245 divider_0/nor_1/Z1 gnd 0.01fF +C246 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF +C247 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF +C248 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF +C249 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF +C250 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF +C251 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF +C252 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF +C253 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF +C254 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF +C255 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF +C256 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF +C257 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF +C258 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF +C259 divider_0/prescaler_0/tspc_1/a_630_n680# gnd 0.61fF +C260 cp_0/a_1710_0# cp_0/out 0.84fF +C261 pd_0/R pd_0/and_pd_0/Out1 0.33fF +C262 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF +C263 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF +C264 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF +C265 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF +C266 divider_0/tspc_1/Z4 gnd 0.44fF +C267 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF +C268 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF +C269 gnd divider_0/tspc_2/Z3 0.27fF +C270 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF +C271 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF +C272 cp_1/a_1710_0# io_analog[1] 0.32fF +C273 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF +C274 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C275 divider_0/tspc_1/a_630_n680# gnd 0.62fF +C276 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF +C277 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF +C278 divider_0/prescaler_0/Out divider_0/clk 0.51fF +C279 pd_0/R pd_0/tspc_r_1/Z2 0.21fF +C280 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF +C281 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF +C282 divider_0/tspc_1/Q gnd 0.33fF +C283 pd_0/UP pd_0/and_pd_0/Z1 0.06fF +C284 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/mc2 0.33fF +C285 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF +C286 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF +C287 divider_0/nor_1/A divider_0/and_0/B 0.08fF +C288 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF +C289 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF +C290 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF +C291 io_analog[0] io_analog[1] 12.30fF +C292 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF +C293 gnd divider_0/and_0/B 0.45fF +C294 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF +C295 divider_0/nor_1/B divider_0/nor_0/B 0.47fF +C296 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF +C297 cp_0/a_1710_0# cp_0/down 0.32fF +C298 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF +C299 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF +C300 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF +C301 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF +C302 divider_0/and_0/OUT divider_0/and_0/B 0.01fF +C303 gnd divider_0/tspc_2/Z4 0.44fF +C304 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF +C305 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF +C306 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF +C307 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF +C308 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF +C309 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF +C310 divider_0/prescaler_0/Out divider_0/tspc_0/Z4 0.12fF +C311 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF +C312 io_clamp_high[1] io_analog[5] 0.53fF +C313 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF +C314 divider_0/tspc_1/Z1 divider_0/tspc_0/Q 0.01fF +C315 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF +C316 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF +C317 divider_0/nor_1/A gnd 1.02fF +C318 cp_0/a_1710_n2840# cp_0/out 0.61fF +C319 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF +C320 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF +C321 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF +C322 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF +C323 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF +C324 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF +C325 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF +C326 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF +C327 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF +C328 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF +C329 divider_0/prescaler_0/tspc_1/Z2 gnd 0.17fF +C330 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF +C331 pd_0/UP pd_0/tspc_r_1/z5 0.03fF +C332 divider_0/tspc_0/a_630_n680# gnd 0.62fF +C333 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF +C334 divider_0/tspc_0/Z1 divider_0/tspc_0/Z4 0.00fF +C335 divider_0/and_0/OUT gnd 0.28fF +C336 divider_0/mc2 divider_0/and_0/B 0.20fF +C337 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF +C338 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF +C339 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF +C340 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF +C341 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF +C342 divider_0/prescaler_0/tspc_0/Z3 gnd 0.27fF +C343 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF +C344 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF +C345 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF +C346 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF +C347 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF +C348 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF +C349 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF +C350 divider_0/and_0/out1 divider_0/and_0/B 0.18fF +C351 cp_0/upbar cp_0/a_1710_n2840# 0.29fF +C352 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF +C353 io_clamp_low[0] io_analog[4] 0.53fF +C354 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF +C355 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF +C356 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF +C357 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF +C358 divider_0/nor_1/B divider_0/and_0/A 0.26fF +C359 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF +C360 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF +C361 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF +C362 divider_0/nor_0/Z1 gnd 0.01fF +C363 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF +C364 divider_0/tspc_0/Z2 divider_0/tspc_0/Z4 0.36fF +C365 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF +C366 divider_0/mc2 divider_0/nor_1/A 0.04fF +C367 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF +C368 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF +C369 divider_0/mc2 gnd 1.36fF +C370 cp_0/a_10_n50# cp_0/vbias 0.19fF +C371 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF +C372 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF +C373 divider_0/tspc_1/Z3 divider_0/tspc_0/Q 0.45fF +C374 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF +C375 divider_0/prescaler_0/tspc_0/D gnd 0.05fF +C376 io_analog[3] cp_1/a_10_n50# 0.22fF +C377 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF +C378 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF +C379 gnd divider_0/and_0/out1 0.23fF +C380 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF +C381 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF +C382 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF +C383 pd_0/DOWN pd_0/R 0.36fF +C384 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF +C385 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF +C386 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF +C387 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF +C388 divider_0/mc2 divider_0/and_0/OUT 0.05fF +C389 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF +C390 io_clamp_low[2] io_clamp_high[2] 0.53fF +C391 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF +C392 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF +C393 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF +C394 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF +C395 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF +C396 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF +C397 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF +C398 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF +C399 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF +C400 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF +C401 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF +C402 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF +C403 gnd divider_0/tspc_2/a_630_n680# 0.61fF +C404 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF +C405 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF +C406 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF +C407 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF +C408 divider_0/nor_0/B divider_0/and_0/B 0.29fF +C409 pd_0/R pd_0/tspc_r_1/Z3 0.29fF +C410 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF +C411 divider_0/prescaler_0/tspc_1/Z3 gnd 0.27fF +C412 divider_0/prescaler_0/nand_0/z1 gnd 0.16fF +C413 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF +C414 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF +C415 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF +C416 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF +Xpd_0 VDD vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd +Xcp_0 cp_0/vbias vdd vssa1 cp_0/out cp_0/down cp_0/upbar cp +Xcp_1 io_analog[3] vdda1 vssa1 io_analog[0] io_analog[1] io_analog[2] cp +Xfilter_0 vssa1 filter +Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4 ++ ro_complete_0/a3 ro_complete_0/a2 ro_complete +Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider +C417 io_analog[4] vdda1 25.05fF +C418 io_analog[5] vdda1 25.05fF +C419 io_analog[6] vdda1 25.05fF +C420 io_in_3v3[0] vdda1 0.61fF +C421 io_oeb[26] vdda1 0.61fF +C422 io_in[0] vdda1 0.61fF +C423 io_out[26] vdda1 0.61fF +C424 io_out[0] vdda1 0.61fF +C425 io_in[26] vdda1 0.61fF +C426 io_oeb[0] vdda1 0.61fF +C427 io_in_3v3[26] vdda1 0.61fF +C428 io_in_3v3[1] vdda1 0.61fF +C429 io_oeb[25] vdda1 0.61fF +C430 io_in[1] vdda1 0.61fF +C431 io_out[25] vdda1 0.61fF +C432 io_out[1] vdda1 0.61fF +C433 io_in[25] vdda1 0.61fF +C434 io_oeb[1] vdda1 0.61fF +C435 io_in_3v3[25] vdda1 0.61fF +C436 io_in_3v3[2] vdda1 0.61fF +C437 io_oeb[24] vdda1 0.61fF +C438 io_in[2] vdda1 0.61fF +C439 io_out[24] vdda1 0.61fF +C440 io_out[2] vdda1 0.61fF +C441 io_in[24] vdda1 0.61fF +C442 io_oeb[2] vdda1 0.61fF +C443 io_in_3v3[24] vdda1 0.61fF +C444 io_in_3v3[3] vdda1 0.61fF +C445 gpio_noesd[17] vdda1 0.61fF +C446 io_in[3] vdda1 0.61fF +C447 gpio_analog[17] vdda1 0.61fF +C448 io_out[3] vdda1 0.61fF +C449 io_oeb[3] vdda1 0.61fF +C450 io_in_3v3[4] vdda1 0.61fF +C451 io_in[4] vdda1 0.61fF +C452 io_out[4] vdda1 0.61fF +C453 io_oeb[4] vdda1 0.61fF +C454 io_oeb[23] vdda1 0.61fF +C455 io_out[23] vdda1 0.61fF +C456 io_in[23] vdda1 0.61fF +C457 io_in_3v3[23] vdda1 0.61fF +C458 gpio_noesd[16] vdda1 0.61fF +C459 gpio_analog[16] vdda1 0.61fF +C460 io_in_3v3[5] vdda1 0.61fF +C461 io_in[5] vdda1 0.61fF +C462 io_out[5] vdda1 0.61fF +C463 io_oeb[5] vdda1 0.61fF +C464 io_oeb[22] vdda1 0.61fF +C465 io_out[22] vdda1 0.61fF +C466 io_in[22] vdda1 0.61fF +C467 io_in_3v3[22] vdda1 0.61fF +C468 gpio_noesd[15] vdda1 0.61fF +C469 gpio_analog[15] vdda1 0.61fF +C470 io_in_3v3[6] vdda1 0.61fF +C471 io_in[6] vdda1 0.61fF +C472 io_out[6] vdda1 0.61fF +C473 io_oeb[6] vdda1 0.61fF +C474 io_oeb[21] vdda1 0.61fF +C475 io_out[21] vdda1 0.61fF +C476 io_in[21] vdda1 0.61fF +C477 io_in_3v3[21] vdda1 0.61fF +C478 gpio_noesd[14] vdda1 0.61fF +C479 gpio_analog[14] vdda1 0.61fF +C480 vssd2 vdda1 13.04fF +C481 vssd1 vdda1 13.04fF +C482 vdda2 vdda1 13.04fF +C483 io_oeb[20] vdda1 0.61fF +C484 io_out[20] vdda1 0.61fF +C485 io_in[20] vdda1 0.61fF +C486 io_in_3v3[20] vdda1 0.61fF +C487 gpio_noesd[13] vdda1 0.61fF +C488 gpio_analog[13] vdda1 0.61fF +C489 gpio_analog[0] vdda1 0.61fF +C490 gpio_noesd[0] vdda1 0.61fF +C491 io_in_3v3[7] vdda1 0.61fF +C492 io_in[7] vdda1 0.61fF +C493 io_out[7] vdda1 0.61fF +C494 io_oeb[7] vdda1 0.61fF +C495 io_oeb[19] vdda1 0.61fF +C496 io_out[19] vdda1 0.61fF +C497 io_in[19] vdda1 0.61fF +C498 io_in_3v3[19] vdda1 0.61fF +C499 gpio_noesd[12] vdda1 0.61fF +C500 gpio_analog[12] vdda1 0.61fF +C501 gpio_analog[1] vdda1 0.61fF +C502 gpio_noesd[1] vdda1 0.61fF +C503 io_in_3v3[8] vdda1 0.61fF +C504 io_in[8] vdda1 0.61fF +C505 io_out[8] vdda1 0.61fF +C506 io_oeb[8] vdda1 0.61fF +C507 io_oeb[18] vdda1 0.61fF +C508 io_out[18] vdda1 0.61fF +C509 io_in[18] vdda1 0.61fF +C510 io_in_3v3[18] vdda1 0.61fF +C511 gpio_noesd[11] vdda1 0.61fF +C512 gpio_analog[11] vdda1 0.61fF +C513 gpio_analog[2] vdda1 0.61fF +C514 gpio_noesd[2] vdda1 0.61fF +C515 io_in_3v3[9] vdda1 0.61fF +C516 io_in[9] vdda1 0.61fF +C517 io_out[9] vdda1 0.61fF +C518 io_oeb[9] vdda1 0.61fF +C519 io_oeb[17] vdda1 0.61fF +C520 io_out[17] vdda1 0.61fF +C521 io_in[17] vdda1 0.61fF +C522 io_in_3v3[17] vdda1 0.61fF +C523 gpio_noesd[10] vdda1 0.61fF +C524 gpio_analog[10] vdda1 0.61fF +C525 gpio_analog[3] vdda1 0.61fF +C526 gpio_noesd[3] vdda1 0.61fF +C527 io_in_3v3[10] vdda1 0.61fF +C528 io_in[10] vdda1 0.61fF +C529 io_out[10] vdda1 0.61fF +C530 io_oeb[10] vdda1 0.61fF +C531 io_oeb[16] vdda1 0.61fF +C532 io_out[16] vdda1 0.61fF +C533 io_in[16] vdda1 0.61fF +C534 io_in_3v3[16] vdda1 0.61fF +C535 gpio_noesd[9] vdda1 0.61fF +C536 gpio_analog[9] vdda1 0.61fF +C537 gpio_analog[4] vdda1 0.61fF +C538 gpio_noesd[4] vdda1 0.61fF +C539 io_in_3v3[11] vdda1 0.61fF +C540 io_in[11] vdda1 0.61fF +C541 io_out[11] vdda1 0.61fF +C542 io_oeb[11] vdda1 0.61fF +C543 io_oeb[15] vdda1 0.61fF +C544 io_out[15] vdda1 0.61fF +C545 io_in[15] vdda1 0.61fF +C546 io_in_3v3[15] vdda1 0.61fF +C547 gpio_noesd[8] vdda1 0.61fF +C548 gpio_analog[8] vdda1 0.61fF +C549 gpio_analog[5] vdda1 0.61fF +C550 gpio_noesd[5] vdda1 0.61fF +C551 io_in_3v3[12] vdda1 0.61fF +C552 io_in[12] vdda1 0.61fF +C553 io_out[12] vdda1 0.61fF +C554 io_oeb[12] vdda1 0.61fF +C555 io_oeb[14] vdda1 0.61fF +C556 io_out[14] vdda1 0.61fF +C557 io_in[14] vdda1 0.61fF +C558 io_in_3v3[14] vdda1 0.61fF +C559 gpio_noesd[7] vdda1 0.61fF +C560 gpio_analog[7] vdda1 0.61fF +C561 vssa2 vdda1 13.04fF +C562 gpio_analog[6] vdda1 0.61fF +C563 gpio_noesd[6] vdda1 0.61fF +C564 io_in_3v3[13] vdda1 0.61fF +C565 io_in[13] vdda1 0.61fF +C566 io_out[13] vdda1 0.61fF +C567 io_oeb[13] vdda1 0.61fF +C568 vccd1 vdda1 13.04fF +C569 vccd2 vdda1 13.04fF +C570 io_analog[10] vdda1 6.83fF +C571 io_clamp_high[0] vdda1 3.58fF +C572 io_clamp_low[0] vdda1 3.58fF +C573 io_clamp_high[1] vdda1 3.58fF +C574 io_clamp_low[1] vdda1 3.58fF +C575 io_clamp_high[2] vdda1 3.58fF +C576 io_clamp_low[2] vdda1 3.58fF +C577 io_analog[7] vdda1 6.83fF +C578 io_analog[8] vdda1 6.83fF +C579 io_analog[9] vdda1 6.83fF +C580 user_irq[2] vdda1 0.63fF +C581 user_irq[1] vdda1 0.63fF +C582 user_irq[0] vdda1 0.63fF +C583 user_clock2 vdda1 0.63fF +C584 la_oenb[127] vdda1 0.63fF +C585 la_data_out[127] vdda1 0.63fF +C586 la_data_in[127] vdda1 0.63fF +C587 la_oenb[126] vdda1 0.63fF +C588 la_data_out[126] vdda1 0.63fF +C589 la_data_in[126] vdda1 0.63fF +C590 la_oenb[125] vdda1 0.63fF +C591 la_data_out[125] vdda1 0.63fF +C592 la_data_in[125] vdda1 0.63fF +C593 la_oenb[124] vdda1 0.63fF +C594 la_data_out[124] vdda1 0.63fF +C595 la_data_in[124] vdda1 0.63fF +C596 la_oenb[123] vdda1 0.63fF +C597 la_data_out[123] vdda1 0.63fF +C598 la_data_in[123] vdda1 0.63fF +C599 la_oenb[122] vdda1 0.63fF +C600 la_data_out[122] vdda1 0.63fF +C601 la_data_in[122] vdda1 0.63fF +C602 la_oenb[121] vdda1 0.63fF +C603 la_data_out[121] vdda1 0.63fF +C604 la_data_in[121] vdda1 0.63fF +C605 la_oenb[120] vdda1 0.63fF +C606 la_data_out[120] vdda1 0.63fF +C607 la_data_in[120] vdda1 0.63fF +C608 la_oenb[119] vdda1 0.63fF +C609 la_data_out[119] vdda1 0.63fF +C610 la_data_in[119] vdda1 0.63fF +C611 la_oenb[118] vdda1 0.63fF +C612 la_data_out[118] vdda1 0.63fF +C613 la_data_in[118] vdda1 0.63fF +C614 la_oenb[117] vdda1 0.63fF +C615 la_data_out[117] vdda1 0.63fF +C616 la_data_in[117] vdda1 0.63fF +C617 la_oenb[116] vdda1 0.63fF +C618 la_data_out[116] vdda1 0.63fF +C619 la_data_in[116] vdda1 0.63fF +C620 la_oenb[115] vdda1 0.63fF +C621 la_data_out[115] vdda1 0.63fF +C622 la_data_in[115] vdda1 0.63fF +C623 la_oenb[114] vdda1 0.63fF +C624 la_data_out[114] vdda1 0.63fF +C625 la_data_in[114] vdda1 0.63fF +C626 la_oenb[113] vdda1 0.63fF +C627 la_data_out[113] vdda1 0.63fF +C628 la_data_in[113] vdda1 0.63fF +C629 la_oenb[112] vdda1 0.63fF +C630 la_data_out[112] vdda1 0.63fF +C631 la_data_in[112] vdda1 0.63fF +C632 la_oenb[111] vdda1 0.63fF +C633 la_data_out[111] vdda1 0.63fF +C634 la_data_in[111] vdda1 0.63fF +C635 la_oenb[110] vdda1 0.63fF +C636 la_data_out[110] vdda1 0.63fF +C637 la_data_in[110] vdda1 0.63fF +C638 la_oenb[109] vdda1 0.63fF +C639 la_data_out[109] vdda1 0.63fF +C640 la_data_in[109] vdda1 0.63fF +C641 la_oenb[108] vdda1 0.63fF +C642 la_data_out[108] vdda1 0.63fF +C643 la_data_in[108] vdda1 0.63fF +C644 la_oenb[107] vdda1 0.63fF +C645 la_data_out[107] vdda1 0.63fF +C646 la_data_in[107] vdda1 0.63fF +C647 la_oenb[106] vdda1 0.63fF +C648 la_data_out[106] vdda1 0.63fF +C649 la_data_in[106] vdda1 0.63fF +C650 la_oenb[105] vdda1 0.63fF +C651 la_data_out[105] vdda1 0.63fF +C652 la_data_in[105] vdda1 0.63fF +C653 la_oenb[104] vdda1 0.63fF +C654 la_data_out[104] vdda1 0.63fF +C655 la_data_in[104] vdda1 0.63fF +C656 la_oenb[103] vdda1 0.63fF +C657 la_data_out[103] vdda1 0.63fF +C658 la_data_in[103] vdda1 0.63fF +C659 la_oenb[102] vdda1 0.63fF +C660 la_data_out[102] vdda1 0.63fF +C661 la_data_in[102] vdda1 0.63fF +C662 la_oenb[101] vdda1 0.63fF +C663 la_data_out[101] vdda1 0.63fF +C664 la_data_in[101] vdda1 0.63fF +C665 la_oenb[100] vdda1 0.63fF +C666 la_data_out[100] vdda1 0.63fF +C667 la_data_in[100] vdda1 0.63fF +C668 la_oenb[99] vdda1 0.63fF +C669 la_data_out[99] vdda1 0.63fF +C670 la_data_in[99] vdda1 0.63fF +C671 la_oenb[98] vdda1 0.63fF +C672 la_data_out[98] vdda1 0.63fF +C673 la_data_in[98] vdda1 0.63fF +C674 la_oenb[97] vdda1 0.63fF +C675 la_data_out[97] vdda1 0.63fF +C676 la_data_in[97] vdda1 0.63fF +C677 la_oenb[96] vdda1 0.63fF +C678 la_data_out[96] vdda1 0.63fF +C679 la_data_in[96] vdda1 0.63fF +C680 la_oenb[95] vdda1 0.63fF +C681 la_data_out[95] vdda1 0.63fF +C682 la_data_in[95] vdda1 0.63fF +C683 la_oenb[94] vdda1 0.63fF +C684 la_data_out[94] vdda1 0.63fF +C685 la_data_in[94] vdda1 0.63fF +C686 la_oenb[93] vdda1 0.63fF +C687 la_data_out[93] vdda1 0.63fF +C688 la_data_in[93] vdda1 0.63fF +C689 la_oenb[92] vdda1 0.63fF +C690 la_data_out[92] vdda1 0.63fF +C691 la_data_in[92] vdda1 0.63fF +C692 la_oenb[91] vdda1 0.63fF +C693 la_data_out[91] vdda1 0.63fF +C694 la_data_in[91] vdda1 0.63fF +C695 la_oenb[90] vdda1 0.63fF +C696 la_data_out[90] vdda1 0.63fF +C697 la_data_in[90] vdda1 0.63fF +C698 la_oenb[89] vdda1 0.63fF +C699 la_data_out[89] vdda1 0.63fF +C700 la_data_in[89] vdda1 0.63fF +C701 la_oenb[88] vdda1 0.63fF +C702 la_data_out[88] vdda1 0.63fF +C703 la_data_in[88] vdda1 0.63fF +C704 la_oenb[87] vdda1 0.63fF +C705 la_data_out[87] vdda1 0.63fF +C706 la_data_in[87] vdda1 0.63fF +C707 la_oenb[86] vdda1 0.63fF +C708 la_data_out[86] vdda1 0.63fF +C709 la_data_in[86] vdda1 0.63fF +C710 la_oenb[85] vdda1 0.63fF +C711 la_data_out[85] vdda1 0.63fF +C712 la_data_in[85] vdda1 0.63fF +C713 la_oenb[84] vdda1 0.63fF +C714 la_data_out[84] vdda1 0.63fF +C715 la_data_in[84] vdda1 0.63fF +C716 la_oenb[83] vdda1 0.63fF +C717 la_data_out[83] vdda1 0.63fF +C718 la_data_in[83] vdda1 0.63fF +C719 la_oenb[82] vdda1 0.63fF +C720 la_data_out[82] vdda1 0.63fF +C721 la_data_in[82] vdda1 0.63fF +C722 la_oenb[81] vdda1 0.63fF +C723 la_data_out[81] vdda1 0.63fF +C724 la_data_in[81] vdda1 0.63fF +C725 la_oenb[80] vdda1 0.63fF +C726 la_data_out[80] vdda1 0.63fF +C727 la_data_in[80] vdda1 0.63fF +C728 la_oenb[79] vdda1 0.63fF +C729 la_data_out[79] vdda1 0.63fF +C730 la_data_in[79] vdda1 0.63fF +C731 la_oenb[78] vdda1 0.63fF +C732 la_data_out[78] vdda1 0.63fF +C733 la_data_in[78] vdda1 0.63fF +C734 la_oenb[77] vdda1 0.63fF +C735 la_data_out[77] vdda1 0.63fF +C736 la_data_in[77] vdda1 0.63fF +C737 la_oenb[76] vdda1 0.63fF +C738 la_data_out[76] vdda1 0.63fF +C739 la_data_in[76] vdda1 0.63fF +C740 la_oenb[75] vdda1 0.63fF +C741 la_data_out[75] vdda1 0.63fF +C742 la_data_in[75] vdda1 0.63fF +C743 la_oenb[74] vdda1 0.63fF +C744 la_data_out[74] vdda1 0.63fF +C745 la_data_in[74] vdda1 0.63fF +C746 la_oenb[73] vdda1 0.63fF +C747 la_data_out[73] vdda1 0.63fF +C748 la_data_in[73] vdda1 0.63fF +C749 la_oenb[72] vdda1 0.63fF +C750 la_data_out[72] vdda1 0.63fF +C751 la_data_in[72] vdda1 0.63fF +C752 la_oenb[71] vdda1 0.63fF +C753 la_data_out[71] vdda1 0.63fF +C754 la_data_in[71] vdda1 0.63fF +C755 la_oenb[70] vdda1 0.63fF +C756 la_data_out[70] vdda1 0.63fF +C757 la_data_in[70] vdda1 0.63fF +C758 la_oenb[69] vdda1 0.63fF +C759 la_data_out[69] vdda1 0.63fF +C760 la_data_in[69] vdda1 0.63fF +C761 la_oenb[68] vdda1 0.63fF +C762 la_data_out[68] vdda1 0.63fF +C763 la_data_in[68] vdda1 0.63fF +C764 la_oenb[67] vdda1 0.63fF +C765 la_data_out[67] vdda1 0.63fF +C766 la_data_in[67] vdda1 0.63fF +C767 la_oenb[66] vdda1 0.63fF +C768 la_data_out[66] vdda1 0.63fF +C769 la_data_in[66] vdda1 0.63fF +C770 la_oenb[65] vdda1 0.63fF +C771 la_data_out[65] vdda1 0.63fF +C772 la_data_in[65] vdda1 0.63fF +C773 la_oenb[64] vdda1 0.63fF +C774 la_data_out[64] vdda1 0.63fF +C775 la_data_in[64] vdda1 0.63fF +C776 la_oenb[63] vdda1 0.63fF +C777 la_data_out[63] vdda1 0.63fF +C778 la_data_in[63] vdda1 0.63fF +C779 la_oenb[62] vdda1 0.63fF +C780 la_data_out[62] vdda1 0.63fF +C781 la_data_in[62] vdda1 0.63fF +C782 la_oenb[61] vdda1 0.63fF +C783 la_data_out[61] vdda1 0.63fF +C784 la_data_in[61] vdda1 0.63fF +C785 la_oenb[60] vdda1 0.63fF +C786 la_data_out[60] vdda1 0.63fF +C787 la_data_in[60] vdda1 0.63fF +C788 la_oenb[59] vdda1 0.63fF +C789 la_data_out[59] vdda1 0.63fF +C790 la_data_in[59] vdda1 0.63fF +C791 la_oenb[58] vdda1 0.63fF +C792 la_data_out[58] vdda1 0.63fF +C793 la_data_in[58] vdda1 0.63fF +C794 la_oenb[57] vdda1 0.63fF +C795 la_data_out[57] vdda1 0.63fF +C796 la_data_in[57] vdda1 0.63fF +C797 la_oenb[56] vdda1 0.63fF +C798 la_data_out[56] vdda1 0.63fF +C799 la_data_in[56] vdda1 0.63fF +C800 la_oenb[55] vdda1 0.63fF +C801 la_data_out[55] vdda1 0.63fF +C802 la_data_in[55] vdda1 0.63fF +C803 la_oenb[54] vdda1 0.63fF +C804 la_data_out[54] vdda1 0.63fF +C805 la_data_in[54] vdda1 0.63fF +C806 la_oenb[53] vdda1 0.63fF +C807 la_data_out[53] vdda1 0.63fF +C808 la_data_in[53] vdda1 0.63fF +C809 la_oenb[52] vdda1 0.63fF +C810 la_data_out[52] vdda1 0.63fF +C811 la_data_in[52] vdda1 0.63fF +C812 la_oenb[51] vdda1 0.63fF +C813 la_data_out[51] vdda1 0.63fF +C814 la_data_in[51] vdda1 0.63fF +C815 la_oenb[50] vdda1 0.63fF +C816 la_data_out[50] vdda1 0.63fF +C817 la_data_in[50] vdda1 0.63fF +C818 la_oenb[49] vdda1 0.63fF +C819 la_data_out[49] vdda1 0.63fF +C820 la_data_in[49] vdda1 0.63fF +C821 la_oenb[48] vdda1 0.63fF +C822 la_data_out[48] vdda1 0.63fF +C823 la_data_in[48] vdda1 0.63fF +C824 la_oenb[47] vdda1 0.63fF +C825 la_data_out[47] vdda1 0.63fF +C826 la_data_in[47] vdda1 0.63fF +C827 la_oenb[46] vdda1 0.63fF +C828 la_data_out[46] vdda1 0.63fF +C829 la_data_in[46] vdda1 0.63fF +C830 la_oenb[45] vdda1 0.63fF +C831 la_data_out[45] vdda1 0.63fF +C832 la_data_in[45] vdda1 0.63fF +C833 la_oenb[44] vdda1 0.63fF +C834 la_data_out[44] vdda1 0.63fF +C835 la_data_in[44] vdda1 0.63fF +C836 la_oenb[43] vdda1 0.63fF +C837 la_data_out[43] vdda1 0.63fF +C838 la_data_in[43] vdda1 0.63fF +C839 la_oenb[42] vdda1 0.63fF +C840 la_data_out[42] vdda1 0.63fF +C841 la_data_in[42] vdda1 0.63fF +C842 la_oenb[41] vdda1 0.63fF +C843 la_data_out[41] vdda1 0.63fF +C844 la_data_in[41] vdda1 0.63fF +C845 la_oenb[40] vdda1 0.63fF +C846 la_data_out[40] vdda1 0.63fF +C847 la_data_in[40] vdda1 0.63fF +C848 la_oenb[39] vdda1 0.63fF +C849 la_data_out[39] vdda1 0.63fF +C850 la_data_in[39] vdda1 0.63fF +C851 la_oenb[38] vdda1 0.63fF +C852 la_data_out[38] vdda1 0.63fF +C853 la_data_in[38] vdda1 0.63fF +C854 la_oenb[37] vdda1 0.63fF +C855 la_data_out[37] vdda1 0.63fF +C856 la_data_in[37] vdda1 0.63fF +C857 la_oenb[36] vdda1 0.63fF +C858 la_data_out[36] vdda1 0.63fF +C859 la_data_in[36] vdda1 0.63fF +C860 la_oenb[35] vdda1 0.63fF +C861 la_data_out[35] vdda1 0.63fF +C862 la_data_in[35] vdda1 0.63fF +C863 la_oenb[34] vdda1 0.63fF +C864 la_data_out[34] vdda1 0.63fF +C865 la_data_in[34] vdda1 0.63fF +C866 la_oenb[33] vdda1 0.63fF +C867 la_data_out[33] vdda1 0.63fF +C868 la_data_in[33] vdda1 0.63fF +C869 la_oenb[32] vdda1 0.63fF +C870 la_data_out[32] vdda1 0.63fF +C871 la_data_in[32] vdda1 0.63fF +C872 la_oenb[31] vdda1 0.63fF +C873 la_data_out[31] vdda1 0.63fF +C874 la_data_in[31] vdda1 0.63fF +C875 la_oenb[30] vdda1 0.63fF +C876 la_data_out[30] vdda1 0.63fF +C877 la_data_in[30] vdda1 0.63fF +C878 la_oenb[29] vdda1 0.63fF +C879 la_data_out[29] vdda1 0.63fF +C880 la_data_in[29] vdda1 0.63fF +C881 la_oenb[28] vdda1 0.63fF +C882 la_data_out[28] vdda1 0.63fF +C883 la_data_in[28] vdda1 0.63fF +C884 la_oenb[27] vdda1 0.63fF +C885 la_data_out[27] vdda1 0.63fF +C886 la_data_in[27] vdda1 0.63fF +C887 la_oenb[26] vdda1 0.63fF +C888 la_data_out[26] vdda1 0.63fF +C889 la_data_in[26] vdda1 0.63fF +C890 la_oenb[25] vdda1 0.63fF +C891 la_data_out[25] vdda1 0.63fF +C892 la_data_in[25] vdda1 0.63fF +C893 la_oenb[24] vdda1 0.63fF +C894 la_data_out[24] vdda1 0.63fF +C895 la_data_in[24] vdda1 0.63fF +C896 la_oenb[23] vdda1 0.63fF +C897 la_data_out[23] vdda1 0.63fF +C898 la_data_in[23] vdda1 0.63fF +C899 la_oenb[22] vdda1 0.63fF +C900 la_data_out[22] vdda1 0.63fF +C901 la_data_in[22] vdda1 0.63fF +C902 la_oenb[21] vdda1 0.63fF +C903 la_data_out[21] vdda1 0.63fF +C904 la_data_in[21] vdda1 0.63fF +C905 la_oenb[20] vdda1 0.63fF +C906 la_data_out[20] vdda1 0.63fF +C907 la_data_in[20] vdda1 0.63fF +C908 la_oenb[19] vdda1 0.63fF +C909 la_data_out[19] vdda1 0.63fF +C910 la_data_in[19] vdda1 0.63fF +C911 la_oenb[18] vdda1 0.63fF +C912 la_data_out[18] vdda1 0.63fF +C913 la_data_in[18] vdda1 0.63fF +C914 la_oenb[17] vdda1 0.63fF +C915 la_data_out[17] vdda1 0.63fF +C916 la_data_in[17] vdda1 0.63fF +C917 la_oenb[16] vdda1 0.63fF +C918 la_data_out[16] vdda1 0.63fF +C919 la_data_in[16] vdda1 0.63fF +C920 la_oenb[15] vdda1 0.63fF +C921 la_data_out[15] vdda1 0.63fF +C922 la_data_in[15] vdda1 0.63fF +C923 la_oenb[14] vdda1 0.63fF +C924 la_data_out[14] vdda1 0.63fF +C925 la_data_in[14] vdda1 0.63fF +C926 la_oenb[13] vdda1 0.63fF +C927 la_data_out[13] vdda1 0.63fF +C928 la_data_in[13] vdda1 0.63fF +C929 la_oenb[12] vdda1 0.63fF +C930 la_data_out[12] vdda1 0.63fF +C931 la_data_in[12] vdda1 0.63fF +C932 la_oenb[11] vdda1 0.63fF +C933 la_data_out[11] vdda1 0.63fF +C934 la_data_in[11] vdda1 0.63fF +C935 la_oenb[10] vdda1 0.63fF +C936 la_data_out[10] vdda1 0.63fF +C937 la_data_in[10] vdda1 0.63fF +C938 la_oenb[9] vdda1 0.63fF +C939 la_data_out[9] vdda1 0.63fF +C940 la_data_in[9] vdda1 0.63fF +C941 la_oenb[8] vdda1 0.63fF +C942 la_data_out[8] vdda1 0.63fF +C943 la_data_in[8] vdda1 0.63fF +C944 la_oenb[7] vdda1 0.63fF +C945 la_data_out[7] vdda1 0.63fF +C946 la_data_in[7] vdda1 0.63fF +C947 la_oenb[6] vdda1 0.63fF +C948 la_data_out[6] vdda1 0.63fF +C949 la_data_in[6] vdda1 0.63fF +C950 la_oenb[5] vdda1 0.63fF +C951 la_data_out[5] vdda1 0.63fF +C952 la_data_in[5] vdda1 0.63fF +C953 la_oenb[4] vdda1 0.63fF +C954 la_data_out[4] vdda1 0.63fF +C955 la_data_in[4] vdda1 0.63fF +C956 la_oenb[3] vdda1 0.63fF +C957 la_data_out[3] vdda1 0.63fF +C958 la_data_in[3] vdda1 0.63fF +C959 la_oenb[2] vdda1 0.63fF +C960 la_data_out[2] vdda1 0.63fF +C961 la_data_in[2] vdda1 0.63fF +C962 la_oenb[1] vdda1 0.63fF +C963 la_data_out[1] vdda1 0.63fF +C964 la_data_in[1] vdda1 0.63fF +C965 la_oenb[0] vdda1 0.63fF +C966 la_data_out[0] vdda1 0.63fF +C967 la_data_in[0] vdda1 0.63fF +C968 wbs_dat_o[31] vdda1 0.63fF +C969 wbs_dat_i[31] vdda1 0.63fF +C970 wbs_adr_i[31] vdda1 0.63fF +C971 wbs_dat_o[30] vdda1 0.63fF +C972 wbs_dat_i[30] vdda1 0.63fF +C973 wbs_adr_i[30] vdda1 0.63fF +C974 wbs_dat_o[29] vdda1 0.63fF +C975 wbs_dat_i[29] vdda1 0.63fF +C976 wbs_adr_i[29] vdda1 0.63fF +C977 wbs_dat_o[28] vdda1 0.63fF +C978 wbs_dat_i[28] vdda1 0.63fF +C979 wbs_adr_i[28] vdda1 0.63fF +C980 wbs_dat_o[27] vdda1 0.63fF +C981 wbs_dat_i[27] vdda1 0.63fF +C982 wbs_adr_i[27] vdda1 0.63fF +C983 wbs_dat_o[26] vdda1 0.63fF +C984 wbs_dat_i[26] vdda1 0.63fF +C985 wbs_adr_i[26] vdda1 0.63fF +C986 wbs_dat_o[25] vdda1 0.63fF +C987 wbs_dat_i[25] vdda1 0.63fF +C988 wbs_adr_i[25] vdda1 0.63fF +C989 wbs_dat_o[24] vdda1 0.63fF +C990 wbs_dat_i[24] vdda1 0.63fF +C991 wbs_adr_i[24] vdda1 0.63fF +C992 wbs_dat_o[23] vdda1 0.63fF +C993 wbs_dat_i[23] vdda1 0.63fF +C994 wbs_adr_i[23] vdda1 0.63fF +C995 wbs_dat_o[22] vdda1 0.63fF +C996 wbs_dat_i[22] vdda1 0.63fF +C997 wbs_adr_i[22] vdda1 0.63fF +C998 wbs_dat_o[21] vdda1 0.63fF +C999 wbs_dat_i[21] vdda1 0.63fF +C1000 wbs_adr_i[21] vdda1 0.63fF +C1001 wbs_dat_o[20] vdda1 0.63fF +C1002 wbs_dat_i[20] vdda1 0.63fF +C1003 wbs_adr_i[20] vdda1 0.63fF +C1004 wbs_dat_o[19] vdda1 0.63fF +C1005 wbs_dat_i[19] vdda1 0.63fF +C1006 wbs_adr_i[19] vdda1 0.63fF +C1007 wbs_dat_o[18] vdda1 0.63fF +C1008 wbs_dat_i[18] vdda1 0.63fF +C1009 wbs_adr_i[18] vdda1 0.63fF +C1010 wbs_dat_o[17] vdda1 0.63fF +C1011 wbs_dat_i[17] vdda1 0.63fF +C1012 wbs_adr_i[17] vdda1 0.63fF +C1013 wbs_dat_o[16] vdda1 0.63fF +C1014 wbs_dat_i[16] vdda1 0.63fF +C1015 wbs_adr_i[16] vdda1 0.63fF +C1016 wbs_dat_o[15] vdda1 0.63fF +C1017 wbs_dat_i[15] vdda1 0.63fF +C1018 wbs_adr_i[15] vdda1 0.63fF +C1019 wbs_dat_o[14] vdda1 0.63fF +C1020 wbs_dat_i[14] vdda1 0.63fF +C1021 wbs_adr_i[14] vdda1 0.63fF +C1022 wbs_dat_o[13] vdda1 0.63fF +C1023 wbs_dat_i[13] vdda1 0.63fF +C1024 wbs_adr_i[13] vdda1 0.63fF +C1025 wbs_dat_o[12] vdda1 0.63fF +C1026 wbs_dat_i[12] vdda1 0.63fF +C1027 wbs_adr_i[12] vdda1 0.63fF +C1028 wbs_dat_o[11] vdda1 0.63fF +C1029 wbs_dat_i[11] vdda1 0.63fF +C1030 wbs_adr_i[11] vdda1 0.63fF +C1031 wbs_dat_o[10] vdda1 0.63fF +C1032 wbs_dat_i[10] vdda1 0.63fF +C1033 wbs_adr_i[10] vdda1 0.63fF +C1034 wbs_dat_o[9] vdda1 0.63fF +C1035 wbs_dat_i[9] vdda1 0.63fF +C1036 wbs_adr_i[9] vdda1 0.63fF +C1037 wbs_dat_o[8] vdda1 0.63fF +C1038 wbs_dat_i[8] vdda1 0.63fF +C1039 wbs_adr_i[8] vdda1 0.63fF +C1040 wbs_dat_o[7] vdda1 0.63fF +C1041 wbs_dat_i[7] vdda1 0.63fF +C1042 wbs_adr_i[7] vdda1 0.63fF +C1043 wbs_dat_o[6] vdda1 0.63fF +C1044 wbs_dat_i[6] vdda1 0.63fF +C1045 wbs_adr_i[6] vdda1 0.63fF +C1046 wbs_dat_o[5] vdda1 0.63fF +C1047 wbs_dat_i[5] vdda1 0.63fF +C1048 wbs_adr_i[5] vdda1 0.63fF +C1049 wbs_dat_o[4] vdda1 0.63fF +C1050 wbs_dat_i[4] vdda1 0.63fF +C1051 wbs_adr_i[4] vdda1 0.63fF +C1052 wbs_sel_i[3] vdda1 0.63fF +C1053 wbs_dat_o[3] vdda1 0.63fF +C1054 wbs_dat_i[3] vdda1 0.63fF +C1055 wbs_adr_i[3] vdda1 0.63fF +C1056 wbs_sel_i[2] vdda1 0.63fF +C1057 wbs_dat_o[2] vdda1 0.63fF +C1058 wbs_dat_i[2] vdda1 0.63fF +C1059 wbs_adr_i[2] vdda1 0.63fF +C1060 wbs_sel_i[1] vdda1 0.63fF +C1061 wbs_dat_o[1] vdda1 0.63fF +C1062 wbs_dat_i[1] vdda1 0.63fF +C1063 wbs_adr_i[1] vdda1 0.63fF +C1064 wbs_sel_i[0] vdda1 0.63fF +C1065 wbs_dat_o[0] vdda1 0.63fF +C1066 wbs_dat_i[0] vdda1 0.63fF +C1067 wbs_adr_i[0] vdda1 0.63fF +C1068 wbs_we_i vdda1 0.63fF +C1069 wbs_stb_i vdda1 0.63fF +C1070 wbs_cyc_i vdda1 0.63fF +C1071 wbs_ack_o vdda1 0.63fF +C1072 wb_rst_i vdda1 0.63fF +C1073 wb_clk_i vdda1 0.63fF +C1074 divider_0/and_0/Z1 vdda1 0.33fF +C1075 divider_0/and_0/B vdda1 1.79fF +C1076 divider_0/and_0/A vdda1 1.66fF +C1077 divider_0/and_0/out1 vdda1 2.71fF +C1078 divider_0/tspc_2/Z4 vdda1 0.42fF +C1079 divider_0/Out vdda1 1.31fF +C1080 divider_0/tspc_2/Z3 vdda1 2.00fF +C1081 divider_0/tspc_2/Z2 vdda1 1.29fF +C1082 divider_0/tspc_2/Z1 vdda1 0.99fF +C1083 divider_0/nor_0/B vdda1 5.25fF +C1084 divider_0/tspc_2/a_630_n680# vdda1 0.53fF **FLOATING +C1085 divider_0/tspc_1/Z4 vdda1 0.42fF +C1086 divider_0/tspc_1/Q vdda1 2.79fF +C1087 divider_0/tspc_1/Z3 vdda1 2.00fF +C1088 divider_0/tspc_1/Z2 vdda1 1.29fF +C1089 divider_0/tspc_1/Z1 vdda1 0.99fF +C1090 divider_0/nor_1/B vdda1 5.95fF +C1091 divider_0/tspc_1/a_630_n680# vdda1 0.53fF **FLOATING +C1092 divider_0/tspc_0/Z4 vdda1 0.42fF +C1093 divider_0/tspc_0/Q vdda1 2.81fF +C1094 divider_0/tspc_0/Z3 vdda1 2.00fF +C1095 divider_0/tspc_0/Z2 vdda1 1.30fF +C1096 divider_0/tspc_0/Z1 vdda1 0.99fF +C1097 divider_0/nor_1/A vdda1 6.02fF +C1098 divider_0/tspc_0/a_630_n680# vdda1 0.53fF **FLOATING +C1099 divider_0/clk vdda1 5.56fF +C1100 divider_0/prescaler_0/Out vdda1 4.13fF +C1101 divider_0/prescaler_0/nand_1/z1 vdda1 0.20fF +C1102 gnd vdda1 21.94fF +C1103 divider_0/prescaler_0/tspc_2/D vdda1 2.59fF +C1104 divider_0/prescaler_0/tspc_0/Q vdda1 3.30fF +C1105 divider_0/prescaler_0/tspc_1/Q vdda1 2.78fF +C1106 divider_0/prescaler_0/nand_0/z1 vdda1 0.20fF +C1107 divider_0/prescaler_0/tspc_0/D vdda1 3.07fF +C1108 divider_0/and_0/OUT vdda1 5.35fF +C1109 divider_0/prescaler_0/tspc_2/Z4 vdda1 0.42fF +C1110 divider_0/prescaler_0/tspc_2/Z3 vdda1 2.00fF +C1111 divider_0/prescaler_0/tspc_2/Z2 vdda1 1.30fF +C1112 divider_0/prescaler_0/tspc_2/Z1 vdda1 0.99fF +C1113 divider_0/prescaler_0/tspc_2/a_630_n680# vdda1 0.53fF **FLOATING +C1114 divider_0/prescaler_0/tspc_2/a_740_n680# vdda1 1.89fF **FLOATING +C1115 divider_0/prescaler_0/tspc_1/Z4 vdda1 0.42fF +C1116 divider_0/prescaler_0/tspc_1/Z3 vdda1 2.00fF +C1117 divider_0/prescaler_0/tspc_1/Z2 vdda1 1.31fF +C1118 divider_0/prescaler_0/tspc_1/Z1 vdda1 0.99fF +C1119 divider_0/prescaler_0/tspc_1/a_630_n680# vdda1 0.53fF **FLOATING +C1120 divider_0/prescaler_0/m1_2700_2190# vdda1 3.99fF **FLOATING +C1121 divider_0/prescaler_0/tspc_0/Z4 vdda1 0.42fF +C1122 divider_0/prescaler_0/tspc_0/Z3 vdda1 2.00fF +C1123 divider_0/prescaler_0/tspc_0/Z2 vdda1 1.30fF +C1124 divider_0/prescaler_0/tspc_0/Z1 vdda1 0.99fF +C1125 divider_0/prescaler_0/tspc_0/a_630_n680# vdda1 0.53fF **FLOATING +C1126 divider_0/prescaler_0/tspc_0/a_740_n680# vdda1 1.89fF **FLOATING +C1127 divider_0/nor_1/Z1 vdda1 1.33fF +C1128 divider_0/nor_0/Z1 vdda1 1.33fF +C1129 divider_0/mc2 vdda1 3.93fF +C1130 ro_complete_0/cbank_2/v vdda1 17.84fF +C1131 ro_complete_0/cbank_2/switch_5/vin vdda1 0.78fF +C1132 ro_complete_0/cbank_2/switch_4/vin vdda1 1.50fF +C1133 ro_complete_0/cbank_2/switch_2/vin vdda1 1.30fF +C1134 ro_complete_0/cbank_2/switch_3/vin vdda1 0.56fF +C1135 ro_complete_0/cbank_2/switch_1/vin vdda1 1.14fF +C1136 ro_complete_0/cbank_2/switch_0/vin vdda1 1.02fF +C1137 ro_complete_0/cbank_1/v vdda1 16.11fF +C1138 ro_complete_0/cbank_1/switch_5/vin vdda1 0.78fF +C1139 ro_complete_0/a0 vdda1 7.88fF +C1140 ro_complete_0/cbank_1/switch_4/vin vdda1 1.50fF +C1141 ro_complete_0/a1 vdda1 5.39fF +C1142 ro_complete_0/cbank_1/switch_2/vin vdda1 1.30fF +C1143 ro_complete_0/a3 vdda1 6.85fF +C1144 ro_complete_0/cbank_1/switch_3/vin vdda1 0.56fF +C1145 ro_complete_0/a2 vdda1 5.48fF +C1146 ro_complete_0/cbank_1/switch_1/vin vdda1 1.14fF +C1147 ro_complete_0/a4 vdda1 5.36fF +C1148 ro_complete_0/cbank_1/switch_0/vin vdda1 1.02fF +C1149 ro_complete_0/a5 vdda1 5.19fF +C1150 ro_complete_0/cbank_0/v vdda1 14.98fF +C1151 ro_complete_0/cbank_0/switch_5/vin vdda1 0.78fF +C1152 ro_complete_0/cbank_0/switch_4/vin vdda1 1.50fF +C1153 ro_complete_0/cbank_0/switch_2/vin vdda1 1.30fF +C1154 ro_complete_0/cbank_0/switch_3/vin vdda1 0.56fF +C1155 ro_complete_0/cbank_0/switch_1/vin vdda1 1.14fF +C1156 ro_complete_0/cbank_0/switch_0/vin vdda1 1.02fF +C1157 ro_complete_0/ro_var_extend_0/vcont vdda1 0.57fF +C1158 filter_0/a_3976_n5230# vdda1 415.26fF **FLOATING +C1159 filter_0/a_3976_n2998# vdda1 1.34fF **FLOATING +C1160 io_analog[1] vdda1 108.63fF +C1161 io_analog[3] vdda1 197.37fF +C1162 io_analog[0] vdda1 74.25fF +C1163 io_analog[2] vdda1 108.15fF +C1164 cp_1/a_7110_n2840# vdda1 0.17fF **FLOATING +C1165 cp_1/a_3060_n2840# vdda1 1.71fF **FLOATING +C1166 cp_1/a_7110_0# vdda1 0.17fF **FLOATING +C1167 cp_1/a_6370_0# vdda1 0.40fF **FLOATING +C1168 cp_1/a_3060_0# vdda1 4.15fF **FLOATING +C1169 cp_1/a_1710_0# vdda1 6.63fF **FLOATING +C1170 cp_1/a_10_n50# vdda1 2.96fF **FLOATING +C1171 cp_0/down vdda1 1.54fF +C1172 cp_0/vbias vdda1 2.41fF +C1173 cp_0/out vdda1 5.26fF +C1174 cp_0/upbar vdda1 1.50fF +C1175 cp_0/a_7110_n2840# vdda1 0.17fF **FLOATING +C1176 cp_0/a_3060_n2840# vdda1 1.71fF **FLOATING +C1177 cp_0/a_7110_0# vdda1 0.17fF **FLOATING +C1178 cp_0/a_6370_0# vdda1 0.40fF **FLOATING +C1179 cp_0/a_3060_0# vdda1 1.65fF **FLOATING +C1180 cp_0/a_1710_0# vdda1 5.76fF **FLOATING +C1181 cp_0/a_1710_n2840# vdda1 4.89fF **FLOATING +C1182 cp_0/a_10_n50# vdda1 2.96fF **FLOATING +C1183 pd_0/and_pd_0/Z1 vdda1 0.39fF +C1184 pd_0/and_pd_0/Out1 vdda1 2.22fF +C1185 pd_0/tspc_r_1/z5 vdda1 1.10fF +C1186 pd_0/tspc_r_1/Z4 vdda1 1.07fF +C1187 pd_0/tspc_r_1/Qbar vdda1 0.88fF +C1188 pd_0/tspc_r_1/Z2 vdda1 1.22fF +C1189 pd_0/tspc_r_1/Z1 vdda1 0.67fF +C1190 pd_0/UP vdda1 2.21fF +C1191 pd_0/tspc_r_1/Qbar1 vdda1 1.34fF +C1192 pd_0/tspc_r_1/Z3 vdda1 2.12fF +C1193 pd_0/REF vdda1 1.80fF +C1194 pd_0/tspc_r_0/z5 vdda1 1.10fF +C1195 pd_0/tspc_r_0/Z4 vdda1 1.07fF +C1196 pd_0/R vdda1 3.05fF +C1197 pd_0/tspc_r_0/Qbar vdda1 0.79fF +C1198 pd_0/tspc_r_0/Z2 vdda1 1.22fF +C1199 pd_0/tspc_r_0/Z1 vdda1 0.67fF +C1200 pd_0/DOWN vdda1 3.08fF +C1201 pd_0/tspc_r_0/Qbar1 vdda1 1.34fF +C1202 pd_0/tspc_r_0/Z3 vdda1 2.12fF +C1203 pd_0/DIV vdda1 1.82fF .ends