verilog

verilog/rtl/user_analog_proj_example.v

diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
index 53a1c85..0bfe631 100644
--- a/verilog/rtl/user_analog_proj_example.v
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -134,87 +134,23 @@
     wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
     wire [`ANALOG_PADS-1:0] io_analog;
 
-    // wire [31:0] rdata; 
-    // wire [31:0] wdata;
+    wire analog0, analog2, analog3, analog4;
 
-    // wire valid;
-    // wire [3:0] wstrb;
-
-    wire isupply;	// Independent 3.3V supply
-    wire io16, io15, io12, io11;
-
-    // WB MI A
-    // assign valid = wbs_cyc_i && wbs_stb_i; 
-    // assign wstrb = wbs_sel_i & {4{wbs_we_i}};
-    // assign wbs_dat_o = rdata;
-    // assign wdata = wbs_dat_i;
-
-    // IO --- unused (no need to connect to anything)
-    // assign io_out[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = 0;
-    // assign io_out[14:13] = 11'b0;
-    // assign io_out[10:0] = 11'b0;
-
-    // assign io_oeb[`MPRJ_IO_PADS-`ANALOG_PADS-1:17] = -1;
-    // assign io_oeb[14:13] = 11'b1;
-    // assign io_oeb[10:0] = 11'b1;
-
-    // IO --- enable outputs on 11, 12, 15, and 16
-    assign io_out[12:11] = {io12, io11};
-    assign io_oeb[12:11] = {vssd1, vssd1};
-
-    assign io_out[16:15] = {io16, io15};
-    assign io_oeb[16:15] = {vssd1, vssd1};
-
-    // IRQ
-    assign irq = 3'b000;	// Unused
-
-    // LA --- unused (no need to connect to anything)
-    // assign la_data_out = {128{1'b0}};	// Unused
-
-    // Instantiate the POR.  Connect the digital power to user area 1
-    // VCCD, and connect the analog power to user area 1 VDDA.
-
-    // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3]
-    // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12]
-
-    // cp por1 (
-	//     `ifdef USE_POWER_PINS
-	//         .vdd1v8(),
-    //         .vss,
-    //     `endif
-    //     .out,
-    //     .up,
-    //     .down,
-    //     .vbias			// 1.8V domain output
-    // );
-
-    // Instantiate 2nd POR with the analog power supply on one of the
-    // analog pins.  NOTE:  io_analog[4] = mproj_io[18] and is the same
-    // pad with io_clamp_high/low[0].
-
-    // `ifdef USE_POWER_PINS
-	// assign isupply = io_analog[4];
-    // 	assign io_clamp_high[0] = isupply;
-    // 	assign io_clamp_low[0] = vssa1;
-
-	// // Tie off remaining clamps
-    // 	assign io_clamp_high[2:1] = vssa1;
-    // 	assign io_clamp_low[2:1] = vssa1;
-    // `endif
-
-    // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7]
-    // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16]
-
-    // example_por por2 (
-	// `ifdef USE_POWER_PINS
-	//     .vdd3v3(isupply),
-	//     .vdd1v8(vccd1),
-	//     .vss(vssa1),
-	// `endif
-	// .porb_h(gpio_analog[7]),	// 3.3V domain output
-	// .porb_l(io15),			// 1.8V domain output
-	// .por_l(io16)			// 1.8V domain output
-    // );
+    assign io_analog[0] = analog0;
+    assign io_analog[1] = analog1;
+    assign io_analog[2] = analog2;
+    assign io_analog[3] = analog3;
+    
+    cp por1 (
+	    `ifdef USE_POWER_PINS
+	        .vdd1v8(vdda1),
+            .vss(vssa1),
+        `endif
+        .out(analog0),
+        .up(analog1),
+        .down(analog2),
+        .vbias(analog3)
+    );
 
 endmodule