corrected-pins

verilog/rtl/cp.v

diff --git a/verilog/rtl/cp.v b/verilog/rtl/cp.v
index e86b40c..19bb45c 100644
--- a/verilog/rtl/cp.v
+++ b/verilog/rtl/cp.v
@@ -21,11 +21,11 @@
 
 module cp(
 `ifdef USE_POWER_PINS
-    inout vdd1v8,
-    inout vss,
+    inout vdd,
+    inout gnd,
 `endif
     output out,
-    input up,
+    input upbar,
     input down,
     input vbias
 );

verilog/rtl/user_analog_proj_example.v

diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v
index 0bfe631..164b802 100644
--- a/verilog/rtl/user_analog_proj_example.v
+++ b/verilog/rtl/user_analog_proj_example.v
@@ -143,11 +143,11 @@
     
     cp por1 (
 	    `ifdef USE_POWER_PINS
-	        .vdd1v8(vdda1),
-            .vss(vssa1),
+	        .vdd(vdda1),
+            .gnd(vssa1),
         `endif
         .out(analog0),
-        .up(analog1),
+        .upbar(analog1),
         .down(analog2),
         .vbias(analog3)
     );