ver
diff --git a/verilog/rtl/cp.v b/verilog/rtl/cp.v new file mode 100644 index 0000000..e86b40c --- /dev/null +++ b/verilog/rtl/cp.v
@@ -0,0 +1,34 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +`timescale 1 ns / 1 ps + +// This is just a copy of simple_por.v from the Caravel project, used +// as an analog user project example. + +module cp( +`ifdef USE_POWER_PINS + inout vdd1v8, + inout vss, +`endif + output out, + input up, + input down, + input vbias +); + +endmodule +`default_nettype wire
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por.v deleted file mode 100644 index d318fba..0000000 --- a/verilog/rtl/example_por.v +++ /dev/null
@@ -1,95 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none -`timescale 1 ns / 1 ps - -// This is just a copy of simple_por.v from the Caravel project, used -// as an analog user project example. - -module example_por( -`ifdef USE_POWER_PINS - inout vdd3v3, - inout vdd1v8, - inout vss, -`endif - output porb_h, - output porb_l, - output por_l -); - - wire mid, porb_h; - reg inode; - - // This is a behavioral model! Actual circuit is a resitor dumping - // current (slowly) from vdd3v3 onto a capacitor, and this fed into - // two schmitt triggers for strong hysteresis/glitch tolerance. - - initial begin - inode <= 1'b0; - end - - // Emulate current source on capacitor as a 500ns delay either up or - // down. Note that this is sped way up for verilog simulation; the - // actual circuit is set to a 15ms delay. - - always @(posedge vdd3v3) begin - #500 inode <= 1'b1; - end - always @(negedge vdd3v3) begin - #500 inode <= 1'b0; - end - - // Instantiate two shmitt trigger buffers in series - - sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 ( -`ifdef USE_POWER_PINS - .VPWR(vdd3v3), - .VGND(vss), - .VPB(vdd3v3), - .VNB(vss), -`endif - .A(inode), - .X(mid) - ); - - sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 ( -`ifdef USE_POWER_PINS - .VPWR(vdd3v3), - .VGND(vss), - .VPB(vdd3v3), - .VNB(vss), -`endif - .A(mid), - .X(porb_h) - ); - - sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level ( -`ifdef USE_POWER_PINS - .VPWR(vdd3v3), - .VPB(vdd3v3), - .LVPWR(vdd1v8), - .VNB(vss), - .VGND(vss), -`endif - .A(porb_h), - .X(porb_l) - ); - - // since this is behavioral anyway, but this should be - // replaced by a proper inverter - assign por_l = ~porb_l; -endmodule -`default_nettype wire
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v index 94412da..53a1c85 100644 --- a/verilog/rtl/user_analog_proj_example.v +++ b/verilog/rtl/user_analog_proj_example.v
@@ -15,7 +15,7 @@ `default_nettype none -`include "example_por.v" +`include "cp.v" /* * I/O mapping for analog @@ -177,44 +177,44 @@ // Monitor the 3.3V output with mprj_io[10] = gpio_analog[3] // Monitor the 1.8V outputs with mprj_io[11,12] = io_out[11,12] - example_por por1 ( - `ifdef USE_POWER_PINS - .vdd3v3(vdda1), - .vdd1v8(vccd1), - .vss(vssa1), - `endif - .porb_h(gpio_analog[3]), // 3.3V domain output - .porb_l(io11), // 1.8V domain output - .por_l(io12) // 1.8V domain output - ); + // cp por1 ( + // `ifdef USE_POWER_PINS + // .vdd1v8(), + // .vss, + // `endif + // .out, + // .up, + // .down, + // .vbias // 1.8V domain output + // ); // Instantiate 2nd POR with the analog power supply on one of the // analog pins. NOTE: io_analog[4] = mproj_io[18] and is the same // pad with io_clamp_high/low[0]. - `ifdef USE_POWER_PINS - assign isupply = io_analog[4]; - assign io_clamp_high[0] = isupply; - assign io_clamp_low[0] = vssa1; + // `ifdef USE_POWER_PINS + // assign isupply = io_analog[4]; + // assign io_clamp_high[0] = isupply; + // assign io_clamp_low[0] = vssa1; - // Tie off remaining clamps - assign io_clamp_high[2:1] = vssa1; - assign io_clamp_low[2:1] = vssa1; - `endif + // // Tie off remaining clamps + // assign io_clamp_high[2:1] = vssa1; + // assign io_clamp_low[2:1] = vssa1; + // `endif // Monitor the 3.3V output with mprj_io[25] = gpio_analog[7] // Monitor the 1.8V outputs with mprj_io[26,27] = io_out[15,16] - example_por por2 ( - `ifdef USE_POWER_PINS - .vdd3v3(isupply), - .vdd1v8(vccd1), - .vss(vssa1), - `endif - .porb_h(gpio_analog[7]), // 3.3V domain output - .porb_l(io15), // 1.8V domain output - .por_l(io16) // 1.8V domain output - ); + // example_por por2 ( + // `ifdef USE_POWER_PINS + // .vdd3v3(isupply), + // .vdd1v8(vccd1), + // .vss(vssa1), + // `endif + // .porb_h(gpio_analog[7]), // 3.3V domain output + // .porb_l(io15), // 1.8V domain output + // .por_l(io16) // 1.8V domain output + // ); endmodule